Hi Ali, Are you suggesting to change the BaseCPU.py addTwoLevelCacheHierarchy and pass a width and clock on the line: self.toL2Bus = CoherentBus()
If so, setting the bus clock to self.clock? What about the width? 128-bits? Andreas -----Original Message----- From: Ali Saidi [mailto:[email protected]] Sent: 06 July 2012 15:30 To: gem5 Developer List Cc: Default; Andreas Hansson Subject: Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64 Also, it's not completely clear to me that the l1 l2 bus would be that narrow/slow Otherwise it seems like a good. It's probably at least worth defaulting the l1to@2 bus freq to be the CPU freq. Ali Sent from my ARM powered mobile device On Jul 6, 2012, at 9:10 AM, "Steve Reinhardt" <[email protected]> wrote: > Yes, I suppose since the performance will be changing due to the new bus > architecture, now is as good a time as any to make the change. An > announcement on gem5-users is definitely in order. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
