changeset 496304c8017d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=496304c8017d
description:
Fix: Address a few benign memory leaks
This patch is the result of static analysis identifying a number of
memory leaks. The leaks are all benign as they are a result of not
deallocating memory in the desctructor. The fix still has value as it
removes false positives in the static analysis.
diffstat:
src/base/loader/hex_file.cc | 2 ++
src/cpu/activity.cc | 5 +++++
src/cpu/activity.hh | 1 +
src/cpu/base.cc | 3 +++
src/cpu/o3/regfile.hh | 12 ++++++++++++
src/dev/arm/pl111.cc | 5 +++++
src/dev/arm/pl111.hh | 1 +
src/dev/ethertap.cc | 1 +
src/dev/i8254xGBe.cc | 7 +++++++
src/dev/i8254xGBe.hh | 2 +-
src/dev/ns_gige.cc | 4 +++-
src/mem/cache/mshr.cc | 2 ++
src/mem/cache/tags/fa_lru.cc | 8 ++++++++
src/mem/cache/tags/fa_lru.hh | 1 +
src/mem/cache/tags/iic.cc | 1 +
src/mem/page_table.cc | 1 +
src/sim/serialize.cc | 4 ++++
src/sim/serialize.hh | 1 +
18 files changed, 59 insertions(+), 2 deletions(-)
diffs (251 lines):
diff -r 5f0321c03a26 -r 496304c8017d src/base/loader/hex_file.cc
--- a/src/base/loader/hex_file.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/base/loader/hex_file.cc Mon Jul 09 12:35:30 2012 -0400
@@ -56,6 +56,8 @@
HexFile::~HexFile()
{
+ if (fp != NULL)
+ fclose(fp);
}
bool
diff -r 5f0321c03a26 -r 496304c8017d src/cpu/activity.cc
--- a/src/cpu/activity.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/cpu/activity.cc Mon Jul 09 12:35:30 2012 -0400
@@ -46,6 +46,11 @@
std::memset(stageActive, 0, numStages);
}
+ActivityRecorder::~ActivityRecorder()
+{
+ delete[] stageActive;
+}
+
void
ActivityRecorder::activity()
{
diff -r 5f0321c03a26 -r 496304c8017d src/cpu/activity.hh
--- a/src/cpu/activity.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/cpu/activity.hh Mon Jul 09 12:35:30 2012 -0400
@@ -54,6 +54,7 @@
public:
ActivityRecorder(const std::string &name, int num_stages,
int longest_latency, int count);
+ ~ActivityRecorder();
/** Records that there is activity this cycle. */
void activity();
diff -r 5f0321c03a26 -r 496304c8017d src/cpu/base.cc
--- a/src/cpu/base.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/cpu/base.cc Mon Jul 09 12:35:30 2012 -0400
@@ -243,6 +243,9 @@
BaseCPU::~BaseCPU()
{
+ delete profileEvent;
+ delete[] comLoadEventQueue;
+ delete[] comInstEventQueue;
}
void
diff -r 5f0321c03a26 -r 496304c8017d src/cpu/o3/regfile.hh
--- a/src/cpu/o3/regfile.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/cpu/o3/regfile.hh Mon Jul 09 12:35:30 2012 -0400
@@ -75,6 +75,11 @@
PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs);
+ /**
+ * Destructor to free resources
+ */
+ ~PhysRegFile();
+
//Everything below should be pretty well identical to the normal
//register file that exists within AlphaISA class.
//The duplication is unfortunate but it's better than having
@@ -197,4 +202,11 @@
memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
}
+template <class Impl>
+PhysRegFile<Impl>::~PhysRegFile()
+{
+ delete intRegFile;
+ delete floatRegFile;
+}
+
#endif
diff -r 5f0321c03a26 -r 496304c8017d src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/arm/pl111.cc Mon Jul 09 12:35:30 2012 -0400
@@ -84,6 +84,11 @@
vncserver->setFramebufferAddr(dmaBuffer);
}
+Pl111::~Pl111()
+{
+ delete[] dmaBuffer;
+}
+
// read registers and frame buffer
Tick
Pl111::read(PacketPtr pkt)
diff -r 5f0321c03a26 -r 496304c8017d src/dev/arm/pl111.hh
--- a/src/dev/arm/pl111.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/arm/pl111.hh Mon Jul 09 12:35:30 2012 -0400
@@ -316,6 +316,7 @@
return dynamic_cast<const Params *>(_params);
}
Pl111(const Params *p);
+ ~Pl111();
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
diff -r 5f0321c03a26 -r 496304c8017d src/dev/ethertap.cc
--- a/src/dev/ethertap.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/ethertap.cc Mon Jul 09 12:35:30 2012 -0400
@@ -147,6 +147,7 @@
if (buffer)
delete [] buffer;
+ delete interface;
delete listener;
}
diff -r 5f0321c03a26 -r 496304c8017d src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/i8254xGBe.cc Mon Jul 09 12:35:30 2012 -0400
@@ -122,6 +122,11 @@
txFifo.clear();
}
+IGbE::~IGbE()
+{
+ delete etherInt;
+}
+
void
IGbE::init()
{
@@ -827,6 +832,8 @@
IGbE::DescCache<T>::~DescCache()
{
reset();
+ delete[] fetchBuf;
+ delete[] wbBuf;
}
template<class T>
diff -r 5f0321c03a26 -r 496304c8017d src/dev/i8254xGBe.hh
--- a/src/dev/i8254xGBe.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/i8254xGBe.hh Mon Jul 09 12:35:30 2012 -0400
@@ -518,7 +518,7 @@
}
IGbE(const Params *params);
- ~IGbE() {}
+ ~IGbE();
virtual void init();
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
diff -r 5f0321c03a26 -r 496304c8017d src/dev/ns_gige.cc
--- a/src/dev/ns_gige.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/dev/ns_gige.cc Mon Jul 09 12:35:30 2012 -0400
@@ -135,7 +135,9 @@
}
NSGigE::~NSGigE()
-{}
+{
+ delete interface;
+}
/**
* This is to write to the PCI general configuration registers
diff -r 5f0321c03a26 -r 496304c8017d src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/mem/cache/mshr.cc Mon Jul 09 12:35:30 2012 -0400
@@ -460,4 +460,6 @@
MSHR::~MSHR()
{
+ delete[] targets;
+ delete[] deferredTargets;
}
diff -r 5f0321c03a26 -r 496304c8017d src/mem/cache/tags/fa_lru.cc
--- a/src/mem/cache/tags/fa_lru.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/mem/cache/tags/fa_lru.cc Mon Jul 09 12:35:30 2012 -0400
@@ -98,6 +98,14 @@
//assert(check());
}
+FALRU::~FALRU()
+{
+ if (numCaches)
+ delete[] cacheBoundaries;
+
+ delete[] blks;
+}
+
void
FALRU::regStats(const string &name)
{
diff -r 5f0321c03a26 -r 496304c8017d src/mem/cache/tags/fa_lru.hh
--- a/src/mem/cache/tags/fa_lru.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/mem/cache/tags/fa_lru.hh Mon Jul 09 12:35:30 2012 -0400
@@ -156,6 +156,7 @@
* @param hit_latency The hit latency of the cache.
*/
FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
+ ~FALRU();
/**
* Register the stats for this object.
diff -r 5f0321c03a26 -r 496304c8017d src/mem/cache/tags/iic.cc
--- a/src/mem/cache/tags/iic.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/mem/cache/tags/iic.cc Mon Jul 09 12:35:30 2012 -0400
@@ -160,6 +160,7 @@
delete [] dataStore;
delete [] tagStore;
delete [] sets;
+ delete [] dataBlks;
}
/* register cache stats */
diff -r 5f0321c03a26 -r 496304c8017d src/mem/page_table.cc
--- a/src/mem/page_table.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/mem/page_table.cc Mon Jul 09 12:35:30 2012 -0400
@@ -228,6 +228,7 @@
entry = new TheISA::TlbEntry();
entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
pTable[vaddr] = *entry;
+ delete entry;
++i;
}
}
diff -r 5f0321c03a26 -r 496304c8017d src/sim/serialize.cc
--- a/src/sim/serialize.cc Mon Jul 02 08:21:53 2012 -0400
+++ b/src/sim/serialize.cc Mon Jul 09 12:35:30 2012 -0400
@@ -613,6 +613,10 @@
}
}
+Checkpoint::~Checkpoint()
+{
+ delete db;
+}
bool
Checkpoint::find(const string §ion, const string &entry, string &value)
diff -r 5f0321c03a26 -r 496304c8017d src/sim/serialize.hh
--- a/src/sim/serialize.hh Mon Jul 02 08:21:53 2012 -0400
+++ b/src/sim/serialize.hh Mon Jul 09 12:35:30 2012 -0400
@@ -254,6 +254,7 @@
public:
Checkpoint(const std::string &cpt_dir);
+ ~Checkpoint();
const std::string cptDir;
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