changeset 407c06cd29a3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=407c06cd29a3
description:
Bus: Make the default bus width 8 bytes instead of 64
This patch changes the default bus width to a more sensible 8 bytes
(64 bits), which is in line with most on-chip buses. Although there
are cases where a wider or narrower bus is useful, the 8 bytes is a
good compromise to serve as the default.
This patch changes essentially all statistics, and will be bundled
with the outstanding changes to the bus.
diffstat:
src/mem/Bus.py | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r d33332605782 -r 407c06cd29a3 src/mem/Bus.py
--- a/src/mem/Bus.py Mon Jul 09 12:35:37 2012 -0400
+++ b/src/mem/Bus.py Mon Jul 09 12:35:38 2012 -0400
@@ -49,7 +49,7 @@
master = VectorMasterPort("vector port for connecting slaves")
clock = Param.Clock("1GHz", "bus clock speed")
header_cycles = Param.Int(1, "cycles of overhead per transaction")
- width = Param.Int(64, "bus width (bytes)")
+ width = Param.Int(8, "bus width (bytes)")
block_size = Param.Int(64, "The default block size if not set by " \
"any connected module")
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
