changeset 8971a998190a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8971a998190a
description:
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 8 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 3016 +++---
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 6 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 1514 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
| 8 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
| 28 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1598 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 8 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 1 -
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2964 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 8 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1568 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 6 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1782 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
| 2 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
| 9 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
| 192 +-
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
| 554 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
| 1138 +-
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
| 188 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 1112 +-
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
| 186 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 1018 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
| 188 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
| 7 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 986 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 186 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 1144 +-
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 180 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
| 6 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
| 194 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
| 9 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 1100 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 182 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
| 1 -
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1150 +-
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
| 190 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1142 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
| 188 +-
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
| 4 +-
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
| 6 +-
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
| 564 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 1024 +-
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
| 6 +-
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
| 176 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
| 1040 +-
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
| 176 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 1132 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
| 6 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
| 186 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 1218 +-
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
| 184 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
| 692 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 1090 +-
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
| 188 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 1150 +-
tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
| 188 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
| 6 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
| 206 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
| 668 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 1130 +-
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
| 184 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 1172 +-
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
| 190 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 172 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
| 590 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 1052 +-
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
| 160 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 1158 +-
tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
| 110 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
| 6 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
| 12 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
| 64 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 988 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 156 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 2032 ++--
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 6 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 976 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
| 6 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1728 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 6 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 936 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 1146 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
| 444 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
| 990 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
| 842 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
| 60 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
| 4 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
| 6 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
| 943 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
| 943 +-
tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
| 62 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
| 460 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
| 904 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
| 6 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
| 952 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
| 462 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
| 942 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
| 64 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
| 6 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 1221 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
| 4 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
| 8 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
| 454 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
| 4 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
| 6 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
| 916 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 64 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
| 4 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
| 76 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 3860 +++++-----
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
| 4 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
| 84 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 1823 ++--
tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
| 146 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
| 6 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
| 2859 +++---
249 files changed, 34082 insertions(+), 34090 deletions(-)
diffs (truncated from 80918 to 300 lines):
diff -r 0e6bd7082fac -r 8971a998190a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Mon Jul 09 12:35:39 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Mon Jul 09 12:35:41 2012 -0400
@@ -941,7 +941,7 @@
clock=1000
header_cycles=1
use_default_range=true
-width=64
+width=8
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio
system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio
system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio
system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio
system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio
system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio
system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio
system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio
system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio
system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio
system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio
system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio
system.tsunami.ide.config system.tsunami.ethernet.pio
system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -1003,7 +1003,7 @@
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -1060,7 +1060,7 @@
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
diff -r 0e6bd7082fac -r 8971a998190a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Mon Jul 09 12:35:39 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Mon Jul 09 12:35:41 2012 -0400
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:47:55
+gem5 compiled Jul 2 2012 08:30:56
+gem5 started Jul 2 2012 11:07:21
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d
build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py
build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 106801000
-Exiting @ tick 1896395899500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 112168000
+Exiting @ tick 1900530800500 because m5_exit instruction encountered
diff -r 0e6bd7082fac -r 8971a998190a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Jul 09 12:35:39 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Jul 09 12:35:41 2012 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.896396 #
Number of seconds simulated
-sim_ticks 1896395899500 #
Number of ticks simulated
-final_tick 1896395899500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.900531 #
Number of seconds simulated
+sim_ticks 1900530800500 #
Number of ticks simulated
+final_tick 1900530800500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 196112 #
Simulator instruction rate (inst/s)
-host_op_rate 196112 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6628227410 #
Simulator tick rate (ticks/s)
-host_mem_usage 302056 #
Number of bytes of host memory used
-host_seconds 286.11 #
Real time elapsed on the host
-sim_insts 56109524 #
Number of instructions simulated
-sim_ops 56109524 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 881728 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24808704 #
Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650688 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 99648 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 472640 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 28913408 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 881728 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 99648 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 981376 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7865856 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7865856 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13777 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 387636 #
Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41417 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1557 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 7385 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 451772 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122904 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 122904 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 464949 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13082028 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1397750 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 52546 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 249231 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15246504 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 464949 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 52546 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 517495 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4147792 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4147792 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4147792 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 464949 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13082028 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1397750 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 52546 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 249231 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19394296 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 344859 #
number of replacements
-system.l2c.tagsinuse 65321.127934 #
Cycle average of tags in use
-system.l2c.total_refs 2609636 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 410035 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 6.364423 #
Average number of references to valid blocks.
-system.l2c.warmup_cycle 6312493000 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53767.491128 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5338.607060 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6047.920982 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 140.590955 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 26.517809 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.820427 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.081461 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.092284 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.002145 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000405 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996721 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 978177 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 784326 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 102747 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 33274 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1898524 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 832872 #
number of Writeback hits
-system.l2c.Writeback_hits::total 832872 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 159 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 41 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 200 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 29 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 22 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 51 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 175658 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 7994 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 183652 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 978177 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 959984 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 102747 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 41268 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2082176 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 978177 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 959984 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 102747 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 41268 #
number of overall hits
-system.l2c.overall_hits::total 2082176 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13779 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 273160 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1574 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 765 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 289278 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2448 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 557 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3005 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 42 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 80 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 122 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 114897 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 6716 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 121613 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13779 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 388057 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1574 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 7481 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 410891 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13779 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 388057 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1574 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 7481 #
number of overall misses
-system.l2c.overall_misses::total 410891 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 720793500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 14208419500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 82364000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 41213000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 15052790000 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 2256000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 1409000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 3665000 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 419000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 157000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 576000
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6027292500
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 352112000
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6379404500 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 720793500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 20235712000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 82364000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 393325000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21432194500 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 720793500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 20235712000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 82364000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 393325000
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 21432194500 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 991956 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1057486 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 104321 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 34039 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2187802 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 832872 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 832872 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2607 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 598 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3205 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 71
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 102
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 173 #
number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 290555 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 14710 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 305265 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 991956 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1348041 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 104321 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 48749 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2493067 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 991956 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1348041 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 104321 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 48749 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2493067 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.013891 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.258311 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.015088 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.022474 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.132223 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939010
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.931438
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.937598 #
miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591549
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784314
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.705202 #
miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.395440 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.456560 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.398385 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.013891 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.287867 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.015088 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.153460 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.164813 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.013891 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.287867 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.015088 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.153460 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.164813 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52035.723422
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 921.568627
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2529.622980
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1219.633943
# average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9976.190476
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1962.500000
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 4721.311475
# average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52456.600035
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202
# average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52160.291902 #
average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202
# average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52160.291902
# average overall miss latency
+host_inst_rate 119697 #
Simulator instruction rate (inst/s)
+host_op_rate 119697 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3968630665 #
Simulator tick rate (ticks/s)
+host_mem_usage 303044 #
Number of bytes of host memory used
+host_seconds 478.89 #
Real time elapsed on the host
+sim_insts 57321719 #
Number of instructions simulated
+sim_ops 57321719 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 875648 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24657536 #
Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650816 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 107456 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 693056 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 28984512 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 875648 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 107456 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 983104 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7921792 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7921792 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13682 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 385274 #
Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41419 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1679 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10829 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 452883 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123778 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 123778 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 460739 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12974026 #
Total read bandwidth from this memory (bytes/s)
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
