changeset 27d56b644e78 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=27d56b644e78
description:
ruby: tag and data cache access support
Updates to Ruby to support statistics counting of cache accesses. This
feature
serves multiple purposes beyond simple stats collection. It provides
the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.
diffstat:
src/mem/SConscript | 1 +
src/mem/protocol/RubySlicc_Exports.sm | 20 ++++++++++++++
src/mem/protocol/RubySlicc_Types.sm | 6 +++-
src/mem/ruby/system/CacheMemory.cc | 48 ++++++++++++++++++++++++++++++++++
src/mem/ruby/system/CacheMemory.hh | 10 +++++++
src/mem/ruby/system/DMASequencer.cc | 7 ++++
src/mem/ruby/system/DMASequencer.hh | 3 ++
src/mem/ruby/system/DirectoryMemory.cc | 7 ++++
src/mem/ruby/system/DirectoryMemory.hh | 3 ++
src/mem/ruby/system/MemoryControl.cc | 7 ++++
src/mem/ruby/system/MemoryControl.hh | 3 ++
src/mem/ruby/system/Sequencer.cc | 8 +++++
src/mem/ruby/system/Sequencer.hh | 3 ++
src/mem/slicc/ast/TransitionDeclAST.py | 13 +++++++-
src/mem/slicc/ast/TypeFieldEnumAST.py | 9 +++++-
src/mem/slicc/parser.py | 12 +++++++-
src/mem/slicc/symbols/RequestType.py | 33 +++++++++++++++++++++++
src/mem/slicc/symbols/StateMachine.py | 20 ++++++++++++++
src/mem/slicc/symbols/Transition.py | 3 +-
src/mem/slicc/symbols/__init__.py | 1 +
20 files changed, 210 insertions(+), 7 deletions(-)
diffs (truncated from 574 to 300 lines):
diff -r 956796e06b7f -r 27d56b644e78 src/mem/SConscript
--- a/src/mem/SConscript Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/SConscript Tue Jul 10 22:51:54 2012 -0700
@@ -85,6 +85,7 @@
DebugFlag('RubySlicc')
DebugFlag('RubySystem')
DebugFlag('RubyTester')
+DebugFlag('RubyStats')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
diff -r 956796e06b7f -r 27d56b644e78 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Jul 10 22:51:54 2012 -0700
@@ -138,6 +138,7 @@
}
enumeration(SequencerRequestType, desc="...",
default="SequencerRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby
object";
LD, desc="Load";
ST, desc="Store";
NULL, desc="Invalid request type";
@@ -176,6 +177,25 @@
NULL, desc="null request type";
}
+enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
+ DataArrayRead, desc="Read access to the cache's data array";
+ DataArrayWrite, desc="Write access to the cache's data array";
+ TagArrayRead, desc="Read access to the cache's tag array";
+ TagArrayWrite, desc="Write access to the cache's tag array";
+}
+
+enumeration(DirectoryRequestType, desc="...",
default="DirectoryRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the Directory
Ruby object";
+}
+
+enumeration(DMASequencerRequestType, desc="...",
default="DMASequencerRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby
object";
+}
+
+enumeration(MemoryControlRequestType, desc="...",
default="MemoryControlRequestType_NULL") {
+ Default, desc="Replace this with access_types passed to the DMA Ruby
object";
+}
+
enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL")
{
L1Cache, desc="L1 Cache Mach";
L2Cache, desc="L2 Cache Mach";
diff -r 956796e06b7f -r 27d56b644e78 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/protocol/RubySlicc_Types.sm Tue Jul 10 22:51:54 2012 -0700
@@ -108,6 +108,7 @@
void checkCoherence(Address);
void profileNack(Address, int, int, uint64);
void evictionCallback(Address);
+ void recordRequestType(SequencerRequestType);
}
structure(RubyRequest, desc="...", interface="Message", external="yes") {
@@ -130,6 +131,7 @@
AbstractEntry lookup(Address);
bool isPresent(Address);
void invalidateBlock(Address);
+ void recordRequestType(DirectoryRequestType);
}
structure(AbstractCacheEntry, primitive="yes", external = "yes") {
@@ -151,6 +153,7 @@
PrefetchBit);
void setMRU(Address);
+ void recordRequestType(CacheRequestType);
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
@@ -158,12 +161,13 @@
}
structure (MemoryControl, inport="yes", outport="yes", external = "yes") {
-
+ void recordRequestType(CacheRequestType);
}
structure (DMASequencer, external = "yes") {
void ackCallback();
void dataCallback(DataBlock);
+ void recordRequestType(CacheRequestType);
}
structure (TimerTable, inport="yes", external = "yes") {
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/CacheMemory.cc
--- a/src/mem/ruby/system/CacheMemory.cc Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/CacheMemory.cc Tue Jul 10 22:51:54 2012 -0700
@@ -29,6 +29,7 @@
#include "base/intmath.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyCacheTrace.hh"
+#include "debug/RubyStats.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/system/CacheMemory.hh"
#include "mem/ruby/system/System.hh"
@@ -476,3 +477,50 @@
return m_cache[cacheSet][loc]->m_locked == context;
}
+void
+CacheMemory::recordRequestType(CacheRequestType requestType) {
+ DPRINTF(RubyStats, "Recorded statistic: %s\n",
+ CacheRequestType_to_string(requestType));
+ switch(requestType) {
+ case CacheRequestType_DataArrayRead:
+ numDataArrayReads++;
+ return;
+ case CacheRequestType_DataArrayWrite:
+ numDataArrayWrites++;
+ return;
+ case CacheRequestType_TagArrayRead:
+ numTagArrayReads++;
+ return;
+ case CacheRequestType_TagArrayWrite:
+ numTagArrayWrites++;
+ return;
+ default:
+ warn("CacheMemory access_type not found: %s",
+ CacheRequestType_to_string(requestType));
+ }
+}
+
+void
+CacheMemory::regStats() {
+ using namespace Stats;
+
+ numDataArrayReads
+ .name(name() + ".num_data_array_reads")
+ .desc("number of data array reads")
+ ;
+
+ numDataArrayWrites
+ .name(name() + ".num_data_array_writes")
+ .desc("number of data array writes")
+ ;
+
+ numTagArrayReads
+ .name(name() + ".num_tag_array_reads")
+ .desc("number of tag array reads")
+ ;
+
+ numTagArrayWrites
+ .name(name() + ".num_tag_array_writes")
+ .desc("number of tag array writes")
+ ;
+}
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/CacheMemory.hh Tue Jul 10 22:51:54 2012 -0700
@@ -34,6 +34,8 @@
#include <vector>
#include "base/hashmap.hh"
+#include "base/statistics.hh"
+#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/DataBlock.hh"
@@ -115,6 +117,14 @@
void clearStats() const;
void printStats(std::ostream& out) const;
+ void recordRequestType(CacheRequestType requestType);
+ void regStats();
+
+ Stats::Scalar numDataArrayReads;
+ Stats::Scalar numDataArrayWrites;
+ Stats::Scalar numTagArrayReads;
+ Stats::Scalar numTagArrayWrites;
+
private:
// convert a Address to its location in the cache
Index addressToCacheSet(const Address& address) const;
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/DMASequencer.cc Tue Jul 10 22:51:54 2012 -0700
@@ -27,6 +27,7 @@
*/
#include "debug/RubyDma.hh"
+#include "debug/RubyStats.hh"
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
@@ -168,6 +169,12 @@
{
}
+void
+DMASequencer::recordRequestType(DMASequencerRequestType requestType) {
+ DPRINTF(RubyStats, "Recorded statistic: %s\n",
+ DMASequencerRequestType_to_string(requestType));
+}
+
DMASequencer *
DMASequencerParams::create()
{
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/DMASequencer.hh
--- a/src/mem/ruby/system/DMASequencer.hh Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/DMASequencer.hh Tue Jul 10 22:51:54 2012 -0700
@@ -31,6 +31,7 @@
#include <ostream>
+#include "mem/protocol/DMASequencerRequestType.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "params/DMASequencer.hh"
@@ -65,6 +66,8 @@
void printConfig(std::ostream & out);
+ void recordRequestType(DMASequencerRequestType requestType);
+
private:
void issueNext();
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/DirectoryMemory.cc
--- a/src/mem/ruby/system/DirectoryMemory.cc Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/DirectoryMemory.cc Tue Jul 10 22:51:54 2012 -0700
@@ -28,6 +28,7 @@
#include "base/intmath.hh"
#include "debug/RubyCache.hh"
+#include "debug/RubyStats.hh"
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
#include "mem/ruby/system/System.hh"
@@ -226,6 +227,12 @@
}
}
+void
+DirectoryMemory::recordRequestType(DirectoryRequestType requestType) {
+ DPRINTF(RubyStats, "Recorded statistic: %s\n",
+ DirectoryRequestType_to_string(requestType));
+}
+
DirectoryMemory *
RubyDirectoryMemoryParams::create()
{
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/DirectoryMemory.hh
--- a/src/mem/ruby/system/DirectoryMemory.hh Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/DirectoryMemory.hh Tue Jul 10 22:51:54 2012 -0700
@@ -33,6 +33,7 @@
#include <string>
#include "mem/ruby/common/Address.hh"
+#include "mem/protocol/DirectoryRequestType.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/system/MemoryVector.hh"
#include "mem/ruby/system/SparseMemory.hh"
@@ -66,6 +67,8 @@
void print(std::ostream& out) const;
void printStats(std::ostream& out) const;
+ void recordRequestType(DirectoryRequestType requestType);
+
private:
// Private copy constructor and assignment operator
DirectoryMemory(const DirectoryMemory& obj);
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/MemoryControl.cc
--- a/src/mem/ruby/system/MemoryControl.cc Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/MemoryControl.cc Tue Jul 10 22:51:54 2012 -0700
@@ -29,6 +29,7 @@
#include "base/cast.hh"
#include "base/cprintf.hh"
+#include "debug/RubyStats.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
@@ -48,6 +49,12 @@
MemoryControl::~MemoryControl() {};
+void
+MemoryControl::recordRequestType(MemoryControlRequestType request) {
+ DPRINTF(RubyStats, "Recorded request: %s\n",
+ MemoryControlRequestType_to_string(request));
+}
+
RubyMemoryControl *
RubyMemoryControlParams::create()
{
diff -r 956796e06b7f -r 27d56b644e78 src/mem/ruby/system/MemoryControl.hh
--- a/src/mem/ruby/system/MemoryControl.hh Tue Jul 10 22:51:54 2012 -0700
+++ b/src/mem/ruby/system/MemoryControl.hh Tue Jul 10 22:51:54 2012 -0700
@@ -35,6 +35,7 @@
#include <string>
#include "mem/protocol/MemoryMsg.hh"
+#include "mem/protocol/MemoryControlRequestType.hh"
#include "mem/ruby/common/Consumer.hh"
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