On Wed, 18 Jul 2012, Hanna Alam wrote:
i guess that this kind of check (if it's indeed performed ) has to be even
earlier than the translate inside the TLB ( src/arch/x86/tlb.cc)
when working in X86 long mode there is a region of addresses that are not
allowed : as it's mentioned in Intel? 64 and IA-32 Architectures Software
Developer?s Manual V3A
IA-32e mode has two sub-mode ( long mode ) in which :
"64-bit mode. While this mode produces 64-bit linear addresses, the
processor
ensures that bits 63:47 of such an address are identical.1 IA-32e paging
does not
use bits 63:48 of such addresses."
and further more :
"...Such an address is called canonical. Use of a non-canonical linear
address in 64-bit mode pro-
duces a general-protection exception (#GP(0)); the processor does not
attempt to translate non-
canonical linear addresses using IA-32e paging."
( picture can be found in WIKI : http://en.wikipedia.org/wiki/X86-64 under
virtual address space details )
hope this is enough to better clarify the question .
Hanna
On Wed, Jul 18, 2012 at 2:14 PM, Nilay Vaish <[email protected]> wrote:
On Wed, 18 Jul 2012, Hanna Alam wrote:
Hello ,
I'm trying to figure out where does gem5 checks if the virtual address is
in the canonical address region .
if you can elaborate a bit on the checking flow ( in X86 long mode ) and
the related files involved .
What's meant by canonical address region? You might want to take a look at
the function translate() in src/arch/x86/tlb.cc.
--
Nilay
Where earlier than the TLB?
One more thing. I just noticed that the original email was sent to
gem5-dev. This discussion should be taking placing on the gem5-users list
instead.
--
Nilay
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