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(Updated July 21, 2012, 5:14 a.m.) Review request for Default. Description (updated) ------- Changeset 9125:c14aa7de9462 --------------------------- Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. Diffs (updated) ----- src/arch/arm/table_walker.hh 2f6f0631af48 src/arch/arm/table_walker.cc 2f6f0631af48 src/arch/arm/tlb.hh 2f6f0631af48 src/arch/arm/tlb.cc 2f6f0631af48 src/arch/x86/interrupts.hh 2f6f0631af48 src/arch/x86/pagetable_walker.hh 2f6f0631af48 src/arch/x86/pagetable_walker.cc 2f6f0631af48 src/arch/x86/tlb.hh 2f6f0631af48 src/arch/x86/tlb.cc 2f6f0631af48 src/cpu/base.hh 2f6f0631af48 src/cpu/base.cc 2f6f0631af48 src/cpu/testers/directedtest/RubyDirectedTester.hh 2f6f0631af48 src/cpu/testers/directedtest/RubyDirectedTester.cc 2f6f0631af48 src/cpu/testers/memtest/memtest.hh 2f6f0631af48 src/cpu/testers/memtest/memtest.cc 2f6f0631af48 src/cpu/testers/networktest/networktest.hh 2f6f0631af48 src/cpu/testers/networktest/networktest.cc 2f6f0631af48 src/cpu/testers/rubytest/RubyTester.hh 2f6f0631af48 src/cpu/testers/rubytest/RubyTester.cc 2f6f0631af48 src/dev/copy_engine.hh 2f6f0631af48 src/dev/copy_engine.cc 2f6f0631af48 src/dev/dma_device.hh 2f6f0631af48 src/dev/dma_device.cc 2f6f0631af48 src/dev/io_device.hh 2f6f0631af48 src/dev/io_device.cc 2f6f0631af48 src/dev/pcidev.hh 2f6f0631af48 src/dev/x86/i82094aa.hh 2f6f0631af48 src/mem/bridge.hh 2f6f0631af48 src/mem/bridge.cc 2f6f0631af48 src/mem/bus.hh 2f6f0631af48 src/mem/bus.cc 2f6f0631af48 src/mem/cache/base.hh 2f6f0631af48 src/mem/cache/base.cc 2f6f0631af48 src/mem/comm_monitor.hh 2f6f0631af48 src/mem/comm_monitor.cc 2f6f0631af48 src/mem/mem_object.hh 2f6f0631af48 src/mem/mem_object.cc 2f6f0631af48 src/mem/port.hh 2f6f0631af48 src/mem/port.cc 2f6f0631af48 src/mem/ruby/system/RubyPort.hh 2f6f0631af48 src/mem/ruby/system/RubyPort.cc 2f6f0631af48 src/mem/simple_mem.hh 2f6f0631af48 src/mem/simple_mem.cc 2f6f0631af48 src/python/swig/pyobject.cc 2f6f0631af48 src/sim/system.hh 2f6f0631af48 src/sim/system.cc 2f6f0631af48 src/sim/tlb.hh 2f6f0631af48 Diff: http://reviews.gem5.org/r/1273/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
