Did you figure out your 1st problem w/altering the time for when a thread switch will happen? I take it from your comments that you have a hardcoded solution for that but you are trying to figure out a general solution to it.
Is that you question or are you now elaborating on a different problem? From your text, it's a little confusing on if you solved the 1st problem and are working on a 2nd or are considering ways for the 1st problem. Lastly, I know some of the memory system code has been refactored (Andreas, Ali?), but as far as I can remember the CacheUnit/CPU has a instruction and data port attached to it. You can traverse one of those port until you get to the Cache and then ask for the latency. But again, I think the ports are changing so I need one of the memory system guys to follow up on that. I'm not sure of a cleaner way to do that but you could also create your own parameter to pass into the CPU, that waits X cycles before declaring a cache miss. On Sun, Jul 22, 2012 at 10:29 AM, Yuval H. Nacson <[email protected]> wrote: > Hello all, > > > > I'm a relatively new user in gem5, but I already have my share of > experience. > > I attached a conversation I had with Korey Sewell (which suggested me to > move to this mailing-list) on the users list about the Switch on cache hit > switching thread every memory access if the cache latency is longer than a > cpu cycle. > > There's an example in the attached conversation. > > > > Now, What I want to do is to create a delay whenever a thread reaches for > memory. For that I want to postpone the tick event of the cpu. Alas, I've > yet to figure out how to reach the cache latency and CPU cycle time from > within the code. > > > > Any suggestions or thought about my proposed solution? > > > > Thanks, > > Yuval > > > > > > Korey: > > Hi Yuval, > > Unfortunately, this isnt something you can switch in the config file > (although it should be), so you'll need to edit some code to get this > working. > > > > First, there is some code in pipeline_stage.cc that says asks an instruction > if it's stalled on memory or not. I'm guessing "inst->isMemStall()". This > function needs not to return true after only 1 cycle. > > > > Second, that function is set to true in cache_unit.cc. In the execute > function, you'll probably see a "inst->setMemStall()" in there if it tries > to complete the access and the data isnt available yet. > > > > What you'll need to do is edit that code in cache_unit.cc to just wait the > necessary amount of cycles before declaring a memory stall. Please move the > conversation to gem5-dev if you want to go the route of submitting the patch > to make the "MemStall" general instead of 1 cycle. > > > > On Mon, Jul 16, 2012 at 10:07 AM, Yuval H. Nacson > <[email protected]> wrote: > >> Hey, > >> > >> > >> > >> In my quest of inorder pipeline I've encountered another problem. > >> > >> I run two threads on a switch on cache miss machine. Also. as opposed > >> to other question I've sent so far, I'm using the 5 stages pipeline > > supplied > >> with the simulator. > >> > >> The Frequency is 2Ghz and I set the cache latency to be 800ps (which > >> is > > more > >> than a clock cycle). > >> > >> > >> > >> Now. In the fourth stage memory request is being sent and in the fifth > > stage > >> the cache is being read. > >> > >> I get the following: > >> > >> > >> > >> 159888500: system.cpu.stage4: [tid:0]: Not blocked, so attempting to > >> run stage. > >> > >> 159888500: system.cpu.stage4: [tid:0]: Processing instruction > >> [sn:41180] > > ldq > >> with PC (0x1200003f0=>0x1200003f4) > >> > >> 159888500: system.cpu.stage4: [tid:0]: [sn:41180]: sending request to > >> system.cpu.dcache_port. > >> > >> 159888500: system.cpu.dcache_port: [tid:0]: [sn:41180]: Updating the > > command > >> for this instruction > >> > >> 159888500: system.cpu.dcache_port: [tid:0]: [sn:41180]: Trying to > > Complete > >> Data Read Access > >> > >> 159888500: system.cpu.dcache_port: STALL: [tid:0]: Data miss from > >> 0x12009ed78 > >> > >> 159888500: system.cpu.stage4: [tid:0]: [sn:41180] request to > >> system.cpu.dcache_port failed. > >> > >> 159888500: system.cpu.stage4: [tid:0] [sn:41180] Detected cache miss. > >> > >> 159888500: system.cpu.stage4: Inserting [tid:0][sn:41180] into switch > > out > >> buffer. > >> > >> 159888500: system.cpu: Scheduling CPU Event (SquashFromMemStall) for > > cycle > >> 159888500, [tid:0]. > >> > >> 159888500: system.cpu.ResourcePool: Ignoring Unrecognized CPU Event > >> (SquashFromMemStall). > >> > >> 159888500: system.cpu.stage4: Suspending [tid:0] due to cache miss. > >> > >> > >> > >> . > >> > >> > >> > >> 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: [slot:4] > >> Waking > > from > >> cache access (vaddr.0x12009ed78, paddr:0x090d78) > >> > >> 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: Processing > >> cache access > >> > >> 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: Bytes loaded > > were: > >> 0000000000000000 > >> > >> 159888800: system.cpu.dcache_port: [tid:0] Waking up from Cache Miss. > >> > >> 159888800: system.cpu: [tid:0]: Activating ... > >> > >> > >> > >> Note the Time differences. > >> > >> I would like to have my cache to have a latency of 2-3 cycles and not > > having > >> the thread switched. Can it be done? > >> > >> > >> > >> Thanks, > >> > >> Yuval > >> > >> > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > -- > > - Korey > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev -- - Korey _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
