changeset c8d4b0595448 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c8d4b0595448
description:
checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading
the
cpu id register failed because the ids did not match, and hence, the
result
of the instruction did not match. this patch ensures that the ids match
so
this instruction does not fail. this problem only seemed to manifest
itself
when multiple cores were in the system, either multi-core, or extra
switched-
out cores present in the system.
diffstat:
src/cpu/o3/O3CPU.py | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (11 lines):
diff -r b6b4d41ba9b9 -r c8d4b0595448 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Fri Jul 27 16:08:04 2012 -0400
+++ b/src/cpu/o3/O3CPU.py Fri Jul 27 16:08:04 2012 -0400
@@ -141,6 +141,7 @@
warnOnlyOnLoadError=True)
self.checker.itb = ArmTLB(size = self.itb.size)
self.checker.dtb = ArmTLB(size = self.dtb.size)
+ self.checker.cpu_id = self.cpu_id
else:
print "ERROR: Checker only supported under ARM ISA!"
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