changeset 275232ad377d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=275232ad377d
description:
stats: update stats for icache change not allowing dirty data
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 2 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 9 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 2568 ++++----
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 2 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 9 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 1424 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
| 4 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
| 33 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
| 7 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 976 ---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 4 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 2 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 8 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2810 ++++-----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 2 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
| 8 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1462 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1658 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
| 123 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
| 2 -
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
| 222 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1034 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
| 8 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1052 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
| 8 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
| 7 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 116 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
| 8 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
| 7 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 84 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 2 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 9 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 1060 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
| 2 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 9 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 506 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 984 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 456 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
| 2 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1624 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 4 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 846 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 24 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 24 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
| 65 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
| 34 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
| 28 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
| 65 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
| 34 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
| 250 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
| 6 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
| 108 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
| 248 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
| 6 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
| 108 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
| 248 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
| 6 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
| 108 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
| 273 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
| 6 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
| 156 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
| 73 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
| 6 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
| 24 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
| 73 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
| 6 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
| 24 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
| 73 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
| 6 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
| 24 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
| 63 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
| 6 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
| 30 +-
108 files changed, 9834 insertions(+), 12300 deletions(-)
diffs (truncated from 28641 to 300 lines):
diff -r 82491f9ed266 -r 275232ad377d
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Fri Jul 27 16:08:05 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Fri Jul 27 16:08:05 2012 -0400
@@ -1005,7 +1005,7 @@
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
diff -r 82491f9ed266 -r 275232ad377d
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Fri Jul 27 16:08:05 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Fri Jul 27 16:08:05 2012 -0400
@@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 11:07:21
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 22:30:48
gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d
build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py
build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 112168000
-Exiting @ tick 1900530800500 because m5_exit instruction encountered
+Exiting @ tick 1900530295500 because m5_exit instruction encountered
diff -r 82491f9ed266 -r 275232ad377d
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Fri Jul 27 16:08:05 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Fri Jul 27 16:08:05 2012 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.900531 #
Number of seconds simulated
-sim_ticks 1900530800500 #
Number of ticks simulated
-final_tick 1900530800500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.900530 #
Number of seconds simulated
+sim_ticks 1900530295500 #
Number of ticks simulated
+final_tick 1900530295500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 119697 #
Simulator instruction rate (inst/s)
-host_op_rate 119697 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3968630665 #
Simulator tick rate (ticks/s)
-host_mem_usage 303044 #
Number of bytes of host memory used
-host_seconds 478.89 #
Real time elapsed on the host
-sim_insts 57321719 #
Number of instructions simulated
-sim_ops 57321719 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 875648 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24657536 #
Number of bytes read from this memory
+host_inst_rate 128893 #
Simulator instruction rate (inst/s)
+host_op_rate 128893 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4273489918 #
Simulator tick rate (ticks/s)
+host_mem_usage 307500 #
Number of bytes of host memory used
+host_seconds 444.73 #
Real time elapsed on the host
+sim_insts 57321882 #
Number of instructions simulated
+sim_ops 57321882 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 875200 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24658176 #
Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 107456 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 693056 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 28984512 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 875648 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 107456 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 983104 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7921792 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7921792 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13682 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 385274 #
Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 108032 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 692736 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 28984960 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 875200 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 108032 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 983232 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7922432 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7922432 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13675 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 385284 #
Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1679 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10829 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 452883 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 123778 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 123778 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 460739 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12974026 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1688 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10824 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 452890 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123788 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 123788 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 460503 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12974366 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1394777 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 56540 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 364664 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15250746 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 460739 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 56540 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 517279 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4168200 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4168200 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4168200 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 460739 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12974026 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 56843 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 364496 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15250986 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 460503 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 56843 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 517346 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4168538 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4168538 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4168538 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 460503 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12974366 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1394777 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 56540 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 364664 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19418945 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 345959 #
number of replacements
-system.l2c.tagsinuse 65264.030293 #
Cycle average of tags in use
-system.l2c.total_refs 2564962 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 411131 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 6.238795 #
Average number of references to valid blocks.
+system.physmem.bw_total::cpu1.inst 56843 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 364496 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19419523 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 345965 #
number of replacements
+system.l2c.tagsinuse 65264.028554 #
Cycle average of tags in use
+system.l2c.total_refs 2565305 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 411137 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 6.239538 #
Average number of references to valid blocks.
system.l2c.warmup_cycle 6370050000 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53566.099176 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5313.179425 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6099.564968 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 209.813021 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 75.373703 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.817354 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.081073 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.093072 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.003201 #
Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 53566.065326 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5313.128544 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 6099.641645 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 209.824884 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 75.368156 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.817353 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.081072 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.093073 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.003202 #
Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.001150 #
Average percentage of cache occupancy
system.l2c.occ_percent::total 0.995850 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 777532 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 689515 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 314287 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 100987 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1882321 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 806312 #
number of Writeback hits
-system.l2c.Writeback_hits::total 806312 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 176 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 440 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 616 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 51 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 30 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 81 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 128023 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 44351 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 172374 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 777532 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 817538 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 314287 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 145338 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2054695 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 777532 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 817538 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 314287 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 145338 #
number of overall hits
-system.l2c.overall_hits::total 2054695 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13684 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 272967 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1696 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 861 #
number of ReadReq misses
+system.l2c.ReadReq_hits::cpu0.inst 778193 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 689575 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 314248 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 100958 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 1882974 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 806039 #
number of Writeback hits
+system.l2c.Writeback_hits::total 806039 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 174 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 439 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 613 #
number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 52 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 31 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 83 #
number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 128167 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 44386 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 172553 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 778193 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 817742 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 314248 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 145344 #
number of demand (read+write) hits
+system.l2c.demand_hits::total 2055527 #
number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 778193 #
number of overall hits
+system.l2c.overall_hits::cpu0.data 817742 #
number of overall hits
+system.l2c.overall_hits::cpu1.inst 314248 #
number of overall hits
+system.l2c.overall_hits::cpu1.data 145344 #
number of overall hits
+system.l2c.overall_hits::total 2055527 #
number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 13677 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 272973 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1705 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 853 #
number of ReadReq misses
system.l2c.ReadReq_misses::total 289208 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2867 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1568 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 4435 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 726 #
number of SCUpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 2871 #
number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1574 #
number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 4445 #
number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 724 #
number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 747 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1473 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 113091 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 10063 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 123154 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13684 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 386058 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1696 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10924 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 412362 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13684 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 386058 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1696 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 10924 #
number of overall misses
-system.l2c.overall_misses::total 412362 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 728665998
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 14214168999
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 90803000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 47077499
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 15080715496 #
number of ReadReq miss cycles
+system.l2c.SCUpgradeReq_misses::total 1471 #
number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 113108 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 10072 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 123180 #
number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 13677 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 386081 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1705 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 10925 #
number of demand (read+write) misses
+system.l2c.demand_misses::total 412388 #
number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 13677 #
number of overall misses
+system.l2c.overall_misses::cpu0.data 386081 #
number of overall misses
+system.l2c.overall_misses::cpu1.inst 1705 #
number of overall misses
+system.l2c.overall_misses::cpu1.data 10925 #
number of overall misses
+system.l2c.overall_misses::total 412388 #
number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 728382998
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 14214430499
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 91270500
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 46668499
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 15080752496 #
number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 22245414 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000
# number of SCUpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914
# number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 22402914 #
number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500
# number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3107000
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 549004499
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6610096496 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 728665998 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 20275260996 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 90803000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 596081998 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21690811992 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 728665998
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 20275260996
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 90803000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 596081998
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 21690811992 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 791216 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 962482 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 315983 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 101848 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2171529 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 806312 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 806312 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 3043 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 2008 #
number of UpgradeReq accesses(hits+misses)
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