Hi,
Fixing this problem so the CPUs work properly is easy. The attached patch
fixes the problem, but, it still breaks the regression because the
regression configs never set the cacheLineSize field I added. There are
kernel loops that iterate in cacheLineSize increments so the stats change.
Solving this problem is a little more tricky than I thought. Even if
getInstPort() didn't return a reference and was able to return NULL,
checking for NULL for the checker and just returning 0 won't work because
the instruction results won't match. A similar problem arises if I try to
check for the CPU name and do a string compare. The checker needs to get
this value from somewhere outside of itself since it technically doesn't
have its own caches. Adding a pointer to its host CPU doesn't seem like the
right choice. Does anybody have any better ideas? The least evil solution I
can come up with is to use this patch and add to it a modification to the
regression configs to set the cacheLineSize param for the CPUs.
diff --git a/configs/example/fs.py b/configs/example/fs.py
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -136,6 +136,8 @@
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
+ if options.caches:
+ test_sys.cpu[i].cacheLineSize = options.cacheline_size
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -226,7 +226,11 @@
//all caches have the same line size in gem5
//4 byte words in ARM
unsigned lineSizeWords =
- tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
+ tc->getCpuPtr()->cacheLineSize / 4;
+
+ if (!lineSizeWords)
+ return 0;
+
unsigned log2LineSizeWords = 0;
while (lineSizeWords >>= 1) {
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -80,6 +80,7 @@
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
numThreads = Param.Unsigned(1, "number of HW thread contexts")
+ cacheLineSize = Param.Int(0, "Cache Line Size")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -120,7 +120,7 @@
_dataMasterId(p->system->getMasterId(name() + ".data")),
interrupts(p->interrupts),
numThreads(p->numThreads), system(p->system),
- phase(p->phase)
+ phase(p->phase), cacheLineSize(p->cacheLineSize)
{
// currentTick = curTick();
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -330,6 +330,8 @@
Tick phase;
+ int cacheLineSize;
+
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -142,6 +142,7 @@
self.checker.itb = ArmTLB(size = self.itb.size)
self.checker.dtb = ArmTLB(size = self.dtb.size)
self.checker.cpu_id = self.cpu_id
+ self.checker.cacheLineSize = self.cacheLineSize
else:
print "ERROR: Checker only supported under ARM ISA!"
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -97,6 +97,7 @@
params->progress_interval = 0;
temp2++;
+ params->cacheLineSize = cacheLineSize;
params->itb = itb;
params->dtb = dtb;
params->system = system;
Thanks,
Tony
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