> On Aug. 9, 2012, 10:09 a.m., Anthony Gutierrez wrote: > > If there are no contentions I think it would be good to ship this and the > > config patch. It makes switching somewhat usable. With this and the config > > that does switching out-of-the-box I think more people would start looking > > at this; the more people using this the better chance the remaining bugs > > will be fixed.
Also, for all ISAs I typically get this kernel panic "Unable to handle kernel paging request at". So, if anyone who has the time and wants to look into this, I think it has something to do with the TLB having no drain functionality, the cache's drain functionality being incorrect, or some state not being correctly copied over on a switch. Just a hunch. - Anthony ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review3253 ----------------------------------------------------------- On Aug. 9, 2012, 7:07 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated Aug. 9, 2012, 7:07 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9148:4c0189120c02 > --------------------------- > O3,ARM: fix some problems with drain/switchout functionality and add Drain > DPRINTFs > > This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA and adds some useful debug print > statements. > > This is an incremental fix as there are still a few bugs/mem leaks with the > switchout code. Particularly when switching from an O3CPU to a > TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA > I haven't encountered any more assertion failures; now the kernel will > typically panic inside of simulation. > > > Diffs > ----- > > src/arch/arm/table_walker.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/arch/arm/table_walker.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/commit_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/cpu.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/fetch_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/lsq_unit.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/simple/timing.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/copy_engine.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/dma_device.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/i8254xGBe.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/bus.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/cache/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/packet_queue.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/ruby/system/RubyPort.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/sim/SConscript 05137f17887eec174fc7706ebe6295992636b8dc > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
