changeset a2370fa5c793 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a2370fa5c793
description:
stats: Update stats for syscall emulation Linux kernel changes.
diffstat:
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
| 8 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 994 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
| 68 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
| 114 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 1002 +-
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 114 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
| 68 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
| 114 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 1004 +-
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 122 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
| 23 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1096 +-
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
| 128 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
| 130 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 112 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
| 68 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
| 12 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
| 110 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
| 12 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 1032 +-
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
| 12 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 110 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
| 210 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
| 938 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
| 88 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 74 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
| 4 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
| 74 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
| 88 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
| 2 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
| 6 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
| 200 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
| 336 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
| 832 +-
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
| 6 +-
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
| 2 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
| 6 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
| 186 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
| 926 +-
tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
| 6 +-
tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
| 460 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
| 2 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
| 6 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
| 186 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
| 908 +-
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 76 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
| 6 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
| 64 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
| 188 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
| 8 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 1189 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
| 2 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
| 8 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
| 356 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
| 8 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
| 582 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
| 4 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
| 6 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
| 76 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
| 8 +-
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 186 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
| 2 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
| 48 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 3485 ++++-----
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
| 6 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
| 8 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
| 274 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
| 2 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
| 8 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 260 +-
160 files changed, 10099 insertions(+), 10112 deletions(-)
diffs (truncated from 26501 to 300 lines):
diff -r ccf40995e142 -r a2370fa5c793
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini Wed Aug
15 10:38:04 2012 -0400
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini Wed Aug
15 10:38:05 2012 -0400
@@ -489,7 +489,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
@@ -512,7 +512,7 @@
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
diff -r ccf40995e142 -r a2370fa5c793
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout Wed Aug 15
10:38:04 2012 -0400
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout Wed Aug 15
10:38:05 2012 -0400
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:54:18
-gem5 started Jul 2 2012 11:32:18
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:42
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d
build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py
build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC/gem5.opt -d
build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py
build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -38,4 +38,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 389181871500 because target called exit()
+Exiting @ tick 389171398000 because target called exit()
diff -r ccf40995e142 -r a2370fa5c793
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt Wed Aug 15
10:38:04 2012 -0400
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt Wed Aug 15
10:38:05 2012 -0400
@@ -1,173 +1,173 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.389182 #
Number of seconds simulated
-sim_ticks 389181871500 #
Number of ticks simulated
-final_tick 389181871500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 0.389171 #
Number of seconds simulated
+sim_ticks 389171398000 #
Number of ticks simulated
+final_tick 389171398000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 233275 #
Simulator instruction rate (inst/s)
-host_op_rate 234010 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64792479 #
Simulator tick rate (ticks/s)
-host_mem_usage 223132 #
Number of bytes of host memory used
-host_seconds 6006.59 #
Real time elapsed on the host
-sim_insts 1401188958 #
Number of instructions simulated
-sim_ops 1405604152 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 78592 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1679360 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 1757952 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 78592 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 78592 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 163456 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 163456 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1228 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26240 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 27468 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2554 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 2554 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 201942 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4315103 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4517045 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 201942 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 201942 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 419999 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 419999 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 419999 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 201942 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4315103 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4937044 #
Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 172352 #
Simulator instruction rate (inst/s)
+host_op_rate 172895 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47869738 #
Simulator tick rate (ticks/s)
+host_mem_usage 232600 #
Number of bytes of host memory used
+host_seconds 8129.80 #
Real time elapsed on the host
+sim_insts 1401188945 #
Number of instructions simulated
+sim_ops 1405604139 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 78528 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1679232 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 1757760 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 78528 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 78528 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 163392 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 163392 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1227 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26238 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 27465 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2553 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 2553 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 201783 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4314891 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4516673 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 201783 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 201783 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 419846 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 419846 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 419846 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 201783 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4314891 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4936519 #
Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 #
Number of system calls
-system.cpu.numCycles 778363744 #
number of cpu cycles simulated
+system.cpu.numCycles 778342797 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.BPredUnit.lookups 98202538 #
Number of BP lookups
-system.cpu.BPredUnit.condPredicted 88418167 #
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3786555 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 66007710 #
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 65666961 #
Number of BTB hits
+system.cpu.BPredUnit.lookups 98197174 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 88413236 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3785239 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 66015510 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 65664831 #
Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1332 #
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 219 #
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 165889798 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1648919647 #
Number of instructions fetch has processed
-system.cpu.fetch.Branches 98202538 #
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65668293 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 330430884 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 21692843 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 264292230 #
Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 125 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2686 #
Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 162826473 #
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 754831 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 778319405 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.124393 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146166 #
Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1336 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 221 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 165881717 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1648798034 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 98197174 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65666167 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 330411204 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 21674066 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 264316799 #
Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 122 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2684 #
Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 162819499 #
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 755607 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 778298464 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.124294 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.146110 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 447888521 57.55% 57.55% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74380250 9.56% 67.10% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37976870 4.88% 71.98% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9085355 1.17% 73.15% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28165073 3.62% 76.77% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18828553 2.42% 79.19% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11512004 1.48% 80.67% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3871007 0.50% 81.16% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146611772 18.84% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28163510 3.62% 76.77% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18828809 2.42% 79.19% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11510131 1.48% 80.67% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3871378 0.50% 81.16% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 778319405 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126165 #
Number of branch fetches per cycle
-system.cpu.fetch.rate 2.118444 #
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 217790097 #
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 214638982 #
Number of cycles decode is blocked
-system.cpu.decode.RunCycles 285156910 #
Number of cycles decode is running
-system.cpu.decode.UnblockCycles 43029734 #
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 17703682 #
Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1642636299 #
Number of instructions handled by decode
-system.cpu.rename.SquashCycles 17703682 #
Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 241734353 #
Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36955708 #
Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 51946820 #
count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 303044657 #
Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126934185 #
Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1631312586 #
Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 31546408 #
Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73332264 #
Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3116970 #
Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1360939473 #
Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2755912805 #
Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2722068159 #
Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 33844646 #
Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1244770452 #
Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 116169021 #
Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2679381 #
count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2694981 #
count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 272918574 #
count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 438732735 #
Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 180262547 #
Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 255381650 #
Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 82499363 #
Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1517064379 #
Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2634738 #
Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1460855259 #
Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 54931 #
Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 113760463 #
Number of squashed instructions iterated over during squash; mainly for
profiling
-system.cpu.iq.iqSquashedOperandsExamined 136767182 #
Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 391067 #
Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 778319405 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.876935 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.427664 #
Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 778298464 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126162 #
Number of branch fetches per cycle
+system.cpu.fetch.rate 2.118344 #
Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 217730423 #
Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 214714894 #
Number of cycles decode is blocked
+system.cpu.decode.RunCycles 285147826 #
Number of cycles decode is running
+system.cpu.decode.UnblockCycles 43019383 #
Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 17685938 #
Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1642518992 #
Number of instructions handled by decode
+system.cpu.rename.SquashCycles 17685938 #
Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 241679768 #
Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36912628 #
Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 51960575 #
count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 303022356 #
Number of cycles rename is running
+system.cpu.rename.UnblockCycles 127037199 #
Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1631180439 #
Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 31545211 #
Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73402474 #
Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3147906 #
Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1360824399 #
Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2755700072 #
Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2721856567 #
Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 33843505 #
Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1244770439 #
Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 116053960 #
Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2679524 #
count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2694715 #
count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 273063750 #
count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 438707438 #
Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 180249753 #
Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 255184370 #
Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 82754828 #
Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1516941659 #
Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2635026 #
Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1460769058 #
Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 54636 #
Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 113641063 #
Number of squashed instructions iterated over during squash; mainly for
profiling
+system.cpu.iq.iqSquashedOperandsExamined 136677185 #
Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 391355 #
Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 778298464 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.876875 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.427909 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
# Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 147026932 18.89% 18.89% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 186493885 23.96% 42.85% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 211074443 27.12% 69.97% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 130841076 16.81% 86.78% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 70678954 9.08% 95.86% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20414805 2.62% 98.49% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7717737 0.99% 99.48% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3979587 0.51% 99.99% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 91986 0.01% 100.00% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 778319405 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 778298464 #
Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 100522 6.26% 6.26% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 166576 10.38% 16.64% #
attempts to use FU when none available
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