changeset 86c0e6ca5e7c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=86c0e6ca5e7c
description:
O3,ARM: fix some problems with drain/switchout functionality and add
Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with
the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the
ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
diffstat:
src/arch/arm/table_walker.cc | 47 +++++++++++++++++++++++++++++-----------
src/arch/arm/table_walker.hh | 5 ++++
src/cpu/base.cc | 10 ++++++-
src/cpu/o3/commit_impl.hh | 3 +-
src/cpu/o3/cpu.cc | 15 +++++++++---
src/cpu/o3/fetch_impl.hh | 7 ++++-
src/cpu/o3/lsq_unit.hh | 5 ++++
src/cpu/simple/timing.cc | 4 ++-
src/dev/copy_engine.cc | 7 +++--
src/dev/dma_device.cc | 11 +++++----
src/dev/i8254xGBe.cc | 9 ++++---
src/mem/bus.cc | 3 ++
src/mem/cache/base.cc | 2 +
src/mem/packet_queue.cc | 6 ++++-
src/mem/port.cc | 12 ++++++++++
src/mem/port.hh | 2 +
src/mem/ruby/system/RubyPort.cc | 5 +++-
src/sim/SConscript | 1 +
18 files changed, 117 insertions(+), 37 deletions(-)
diffs (truncated from 623 to 300 lines):
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Wed Aug 15 10:38:07 2012 -0400
+++ b/src/arch/arm/table_walker.cc Wed Aug 15 10:38:08 2012 -0400
@@ -43,6 +43,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Checkpoint.hh"
+#include "debug/Drain.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "sim/system.hh"
@@ -51,7 +52,7 @@
TableWalker::TableWalker(const Params *p)
: MemObject(p), port(this, params()->sys, params()->min_backoff,
- params()->max_backoff),
+ params()->max_backoff), drainEvent(NULL),
tlb(NULL), currState(NULL), pending(false),
masterId(p->sys->getMasterId(name())),
doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
@@ -64,20 +65,38 @@
;
}
+void
+TableWalker::completeDrain()
+{
+ if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() &&
+ pendingQueue.empty()) {
+ changeState(Drained);
+ DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
+ drainEvent->process();
+ drainEvent = NULL;
+ }
+}
+
unsigned int
TableWalker::drain(Event *de)
{
- if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
- {
+ unsigned int count = port.drain(de);
+
+ if (stateQueueL1.empty() && stateQueueL2.empty() &&
+ pendingQueue.empty()) {
+ changeState(Drained);
+ DPRINTF(Drain, "TableWalker free, no need to drain\n");
+
+ // table walker is drained, but its ports may still need to be drained
+ return count;
+ } else {
+ drainEvent = de;
changeState(Draining);
- DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
- return 1;
- }
- else
- {
- changeState(Drained);
- DPRINTF(Checkpoint, "TableWalker free, no need to drain\n");
- return 0;
+ DPRINTF(Drain, "TableWalker not drained\n");
+
+ // return port drain count plus the table walker itself needs to drain
+ return count + 1;
+
}
}
@@ -86,8 +105,8 @@
{
MemObject::resume();
if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
- delete currState;
- currState = NULL;
+ delete currState;
+ currState = NULL;
}
}
@@ -667,6 +686,7 @@
doL1Descriptor();
stateQueueL1.pop_front();
+ completeDrain();
// Check if fault was generated
if (currState->fault != NoFault) {
currState->transState->finish(currState->fault, currState->req,
@@ -723,6 +743,7 @@
stateQueueL2.pop_front();
+ completeDrain();
pending = false;
nextWalk(currState->tc);
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Wed Aug 15 10:38:07 2012 -0400
+++ b/src/arch/arm/table_walker.hh Wed Aug 15 10:38:08 2012 -0400
@@ -364,6 +364,9 @@
/** Port to issue translation requests from */
SnoopingDmaPort port;
+ /** If we're draining keep the drain event around until we're drained */
+ Event *drainEvent;
+
/** TLB that is initiating these table walks */
TLB *tlb;
@@ -389,6 +392,8 @@
return dynamic_cast<const Params *>(_params);
}
+ /** Checks if all state is cleared and if so, completes drain */
+ void completeDrain();
virtual unsigned int drain(Event *de);
virtual void resume();
virtual MasterPort& getMasterPort(const std::string &if_name,
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/cpu/base.cc
--- a/src/cpu/base.cc Wed Aug 15 10:38:07 2012 -0400
+++ b/src/cpu/base.cc Wed Aug 15 10:38:08 2012 -0400
@@ -385,8 +385,7 @@
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
@@ -418,11 +417,13 @@
assert(old_itb_port);
SlavePort &slavePort = old_itb_port->getSlavePort();
new_itb_port->bind(slavePort);
+ old_itb_port->unBind();
}
if (new_dtb_port && !new_dtb_port->isConnected()) {
assert(old_dtb_port);
SlavePort &slavePort = old_dtb_port->getSlavePort();
new_dtb_port->bind(slavePort);
+ old_dtb_port->unBind();
}
// Checker whether or not we have to transfer CheckerCPU
@@ -444,17 +445,20 @@
assert(old_checker_itb_port);
SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
new_checker_itb_port->bind(slavePort);
+ old_checker_itb_port->unBind();
}
if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
assert(old_checker_dtb_port);
SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
new_checker_dtb_port->bind(slavePort);
+ old_checker_dtb_port->unBind();
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
@@ -469,10 +473,12 @@
// CPU.
if (!getInstPort().isConnected()) {
getInstPort().bind(oldCPU->getInstPort().getSlavePort());
+ oldCPU->getInstPort().unBind();
}
if (!getDataPort().isConnected()) {
getDataPort().bind(oldCPU->getDataPort().getSlavePort());
+ oldCPU->getDataPort().unBind();
}
}
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Wed Aug 15 10:38:07 2012 -0400
+++ b/src/cpu/o3/commit_impl.hh Wed Aug 15 10:38:08 2012 -0400
@@ -631,7 +631,8 @@
wroteToTimeBuffer = false;
_nextStatus = Inactive;
- if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
+ interrupt == NoFault) {
cpu->signalDrained();
drainPending = false;
return;
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Wed Aug 15 10:38:07 2012 -0400
+++ b/src/cpu/o3/cpu.cc Wed Aug 15 10:38:08 2012 -0400
@@ -55,6 +55,7 @@
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
+#include "debug/Drain.hh"
#include "debug/O3CPU.hh"
#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
@@ -260,7 +261,7 @@
if (!deferRegistration) {
_status = Running;
} else {
- _status = Idle;
+ _status = SwitchedOut;
}
if (params->checker) {
@@ -1119,9 +1120,8 @@
DPRINTF(O3CPU, "Switching out\n");
// If the CPU isn't doing anything, then return immediately.
- if (_status == Idle || _status == SwitchedOut) {
+ if (_status == SwitchedOut)
return 0;
- }
drainCount = 0;
fetch.drain();
@@ -1142,6 +1142,8 @@
wakeCPU();
activityRec.activity();
+ DPRINTF(Drain, "CPU not drained\n");
+
return 1;
} else {
return 0;
@@ -1160,7 +1162,7 @@
changeState(SimObject::Running);
- if (_status == SwitchedOut || _status == Idle)
+ if (_status == SwitchedOut)
return;
assert(system->getMemoryMode() == Enums::timing);
@@ -1183,6 +1185,7 @@
BaseCPU::switchOut();
if (drainEvent) {
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
@@ -1237,6 +1240,10 @@
assert(!tickEvent.scheduled() || tickEvent.squashed());
+ FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
+ if (oldO3CPU)
+ globalSeqNum = oldO3CPU->globalSeqNum;
+
// @todo: Figure out how to properly select the tid to put onto
// the active threads list.
ThreadID tid = 0;
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Wed Aug 15 10:38:07 2012 -0400
+++ b/src/cpu/o3/fetch_impl.hh Wed Aug 15 10:38:08 2012 -0400
@@ -132,8 +132,10 @@
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
- for (int i = 0; i < Impl::MaxThreads; i++)
+ for (int i = 0; i < Impl::MaxThreads; i++) {
+ cacheData[i] = NULL;
decoder[i] = new TheISA::Decoder(NULL);
+ }
}
template <class Impl>
@@ -346,7 +348,8 @@
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
+ if (!cacheData[tid])
+ cacheData[tid] = new uint8_t[cacheBlkSize];
cacheDataPC[tid] = 0;
cacheDataValid[tid] = false;
}
diff -r a4faa7dde56c -r 86c0e6ca5e7c src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Wed Aug 15 10:38:07 2012 -0400
+++ b/src/cpu/o3/lsq_unit.hh Wed Aug 15 10:38:08 2012 -0400
@@ -335,6 +335,11 @@
std::memset(data, 0, sizeof(data));
}
+ ~SQEntry()
+ {
+ inst = NULL;
+ }
+
/** Constructs a store queue entry for a given instruction. */
SQEntry(DynInstPtr &_inst)
: inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
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