changeset e0bad9d7bbd6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e0bad9d7bbd6
description:
Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to
the new class ClockedObject, that sits in between the SimObject and
MemObject in the class hierarchy. Although there are currently a fair
amount of MemObjects that do not make use of the clock, they
potentially should do so, e.g. the caches should at some point have
the same clock as the CPU, potentially with a 1:n ratio. This patch
does not introduce any new clock objects or object hierarchies
(clusters, clock domains etc), but is still a step in the direction of
having a more structured approach clock domains.
The most contentious part of this patch is the serialisation of clocks
that some of the modules (but not all) did previously. This
serialisation should not be needed as the clock is set through the
parameters even when restoring from the checkpoint. In other words,
the state is "stored" in the Python code that creates the modules.
The nextCycle methods are also simplified and the clock phase
parameter of the CPU is removed (this could be part of a clock object
once they are introduced).
diffstat:
src/arch/x86/interrupts.cc | 3 +-
src/arch/x86/interrupts.hh | 1 -
src/arch/x86/utility.cc | 4 +-
src/cpu/BaseCPU.py | 3 -
src/cpu/base.cc | 28 +------
src/cpu/base.hh | 24 +-----
src/cpu/testers/memtest/memtest.hh | 2 -
src/cpu/testers/networktest/networktest.hh | 2 -
src/dev/CopyEngine.py | 4 +-
src/dev/Ethernet.py | 6 +-
src/dev/arm/RealView.py | 6 +-
src/dev/arm/pl111.cc | 24 +-----
src/dev/arm/pl111.hh | 7 -
src/dev/arm/timer_cpulocal.cc | 4 +-
src/dev/i8254xGBe.cc | 2 +-
src/dev/i8254xGBe.hh | 2 -
src/dev/ns_gige.cc | 1 -
src/dev/ns_gige.hh | 4 -
src/dev/sinic.cc | 2 +-
src/dev/sinic.hh | 2 -
src/mem/Bus.py | 3 +-
src/mem/MemObject.py | 4 +-
src/mem/bus.cc | 7 +-
src/mem/bus.hh | 2 -
src/mem/mem_object.cc | 2 +-
src/mem/mem_object.hh | 6 +-
src/sim/ClockedObject.py | 45 +++++++++++
src/sim/SConscript | 1 +
src/sim/clocked_object.hh | 118 +++++++++++++++++++++++++++++
29 files changed, 197 insertions(+), 122 deletions(-)
diffs (truncated from 716 to 300 lines):
diff -r 38dd0780322a -r e0bad9d7bbd6 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Tue Aug 21 05:48:52 2012 -0400
+++ b/src/arch/x86/interrupts.cc Tue Aug 21 05:49:01 2012 -0400
@@ -619,7 +619,6 @@
X86ISA::Interrupts::Interrupts(Params * p) :
BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
- clock(0),
apicTimerEvent(this),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
@@ -630,6 +629,8 @@
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this, latency)
{
+ // Override the default clock
+ clock = 0;
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
diff -r 38dd0780322a -r e0bad9d7bbd6 src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh Tue Aug 21 05:48:52 2012 -0400
+++ b/src/arch/x86/interrupts.hh Tue Aug 21 05:49:01 2012 -0400
@@ -89,7 +89,6 @@
* Timing related stuff.
*/
Tick latency;
- Tick clock;
class ApicTimerEvent : public Event
{
diff -r 38dd0780322a -r e0bad9d7bbd6 src/arch/x86/utility.cc
--- a/src/arch/x86/utility.cc Tue Aug 21 05:48:52 2012 -0400
+++ b/src/arch/x86/utility.cc Tue Aug 21 05:49:01 2012 -0400
@@ -173,7 +173,9 @@
interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
-
+
+ // @todo: Control the relative frequency, in this case 16:1, of
+ // the clocks in the Python code
interrupts->setClock(tc->getCpuPtr()->ticks(16));
// TODO Set the SMRAM base address (SMBASE) to 0x00030000
diff -r 38dd0780322a -r e0bad9d7bbd6 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Tue Aug 21 05:48:52 2012 -0400
+++ b/src/cpu/BaseCPU.py Tue Aug 21 05:49:01 2012 -0400
@@ -145,9 +145,6 @@
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
- clock = Param.Clock('1t', "clock speed")
- phase = Param.Latency('0ns', "clock phase")
-
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
icache_port = MasterPort("Instruction Port")
diff -r 38dd0780322a -r e0bad9d7bbd6 src/cpu/base.cc
--- a/src/cpu/base.cc Tue Aug 21 05:48:52 2012 -0400
+++ b/src/cpu/base.cc Tue Aug 21 05:49:01 2012 -0400
@@ -115,15 +115,12 @@
}
BaseCPU::BaseCPU(Params *p, bool is_checker)
- : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+ : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
_instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")),
interrupts(p->interrupts),
- numThreads(p->numThreads), system(p->system),
- phase(p->phase)
+ numThreads(p->numThreads), system(p->system)
{
-// currentTick = curTick();
-
// if Python did not provide a valid ID, do it here
if (_cpuId == -1 ) {
_cpuId = cpuList.size();
@@ -317,27 +314,6 @@
return MemObject::getMasterPort(if_name, idx);
}
-Tick
-BaseCPU::nextCycle()
-{
- Tick next_tick = curTick() - phase + clock - 1;
- next_tick -= (next_tick % clock);
- next_tick += phase;
- return next_tick;
-}
-
-Tick
-BaseCPU::nextCycle(Tick begin_tick)
-{
- Tick next_tick = begin_tick;
- if (next_tick % clock != 0)
- next_tick = next_tick - (next_tick % clock) + clock;
- next_tick += phase;
-
- assert(next_tick >= curTick());
- return next_tick;
-}
-
void
BaseCPU::registerThreadContexts()
{
diff -r 38dd0780322a -r e0bad9d7bbd6 src/cpu/base.hh
--- a/src/cpu/base.hh Tue Aug 21 05:48:52 2012 -0400
+++ b/src/cpu/base.hh Tue Aug 21 05:49:01 2012 -0400
@@ -88,8 +88,7 @@
class BaseCPU : public MemObject
{
protected:
- // CPU's clock period in terms of the number of ticks of curTime.
- Tick clock;
+
// @todo remove me after debugging with legion done
Tick instCnt;
// every cpu has an id, put it in the base cpu
@@ -174,30 +173,11 @@
*/
MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
-// Tick currentTick;
- inline Tick frequency() const { return SimClock::Frequency / clock; }
- inline Tick ticks(int numCycles) const { return clock * numCycles; }
- inline Tick curCycle() const { return curTick() / clock; }
- inline Tick tickToCycles(Tick val) const { return val / clock; }
inline void workItemBegin() { numWorkItemsStarted++; }
inline void workItemEnd() { numWorkItemsCompleted++; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
- /** The next cycle the CPU should be scheduled, given a cache
- * access or quiesce event returning on this cycle. This function
- * may return curTick() if the CPU should run on the current cycle.
- */
- Tick nextCycle();
-
- /** The next cycle the CPU should be scheduled, given a cache
- * access or quiesce event returning on the given Tick. This
- * function may return curTick() if the CPU should run on the
- * current cycle.
- * @param begin_tick The tick that the event is completing on.
- */
- Tick nextCycle(Tick begin_tick);
-
TheISA::MicrocodeRom microcodeRom;
protected:
@@ -328,8 +308,6 @@
System *system;
- Tick phase;
-
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
diff -r 38dd0780322a -r e0bad9d7bbd6 src/cpu/testers/memtest/memtest.hh
--- a/src/cpu/testers/memtest/memtest.hh Tue Aug 21 05:48:52 2012 -0400
+++ b/src/cpu/testers/memtest/memtest.hh Tue Aug 21 05:49:01 2012 -0400
@@ -56,8 +56,6 @@
// register statistics
virtual void regStats();
- inline Tick ticks(int numCycles) const { return numCycles; }
-
// main simulation loop (one cycle)
void tick();
diff -r 38dd0780322a -r e0bad9d7bbd6 src/cpu/testers/networktest/networktest.hh
--- a/src/cpu/testers/networktest/networktest.hh Tue Aug 21 05:48:52
2012 -0400
+++ b/src/cpu/testers/networktest/networktest.hh Tue Aug 21 05:49:01
2012 -0400
@@ -51,8 +51,6 @@
virtual void init();
- inline Tick ticks(int numCycles) const { return numCycles; }
-
// main simulation loop (one cycle)
void tick();
diff -r 38dd0780322a -r e0bad9d7bbd6 src/dev/CopyEngine.py
--- a/src/dev/CopyEngine.py Tue Aug 21 05:48:52 2012 -0400
+++ b/src/dev/CopyEngine.py Tue Aug 21 05:49:01 2012 -0400
@@ -52,8 +52,8 @@
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that
are supported")
-
- clock = Param.Clock('500MHz', "Clock speed of the device")
+ # Override the default clock
+ clock = '500MHz'
latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is
seen before it's proccessed")
latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is
complete before it's reported as such")
diff -r 38dd0780322a -r e0bad9d7bbd6 src/dev/Ethernet.py
--- a/src/dev/Ethernet.py Tue Aug 21 05:48:52 2012 -0400
+++ b/src/dev/Ethernet.py Tue Aug 21 05:49:01 2012 -0400
@@ -79,7 +79,8 @@
"Number of enteries in the rx descriptor cache")
tx_desc_cache_size = Param.Int(64,
"Number of enteries in the rx descriptor cache")
- clock = Param.Clock('500MHz', "Clock speed of the device")
+ # Override the default clock
+ clock = '500MHz'
VendorID = 0x8086
SubsystemID = 0x1008
SubsystemVendorID = 0x8086
@@ -127,7 +128,8 @@
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- clock = Param.Clock('0ns', "State machine processor frequency")
+ # Override the default clock
+ clock = '0ns'
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff -r 38dd0780322a -r e0bad9d7bbd6 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py Tue Aug 21 05:48:52 2012 -0400
+++ b/src/dev/arm/RealView.py Tue Aug 21 05:49:01 2012 -0400
@@ -118,7 +118,8 @@
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to
GIC")
- clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
+ # Override the default clock
+ clock = '1GHz'
class PL031(AmbaIntDevice):
type = 'PL031'
@@ -134,7 +135,8 @@
class Pl111(AmbaDmaDevice):
type = 'Pl111'
- clock = Param.Clock('24MHz', "Clock speed of the input")
+ # Override the default clock
+ clock = '24MHz'
vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer
display")
amba_id = 0x00141111
diff -r 38dd0780322a -r e0bad9d7bbd6 src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc Tue Aug 21 05:48:52 2012 -0400
+++ b/src/dev/arm/pl111.cc Tue Aug 21 05:49:01 2012 -0400
@@ -63,7 +63,7 @@
lcdRis(0), lcdMis(0),
clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
- clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0), clock(p->clock),
+ clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
vncserver(p->vnc), bmp(NULL), width(LcdMaxWidth), height(LcdMaxHeight),
bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
waterMark(0), dmaPendingNum(0), readEvent(this), fillFifoEvent(this),
@@ -512,26 +512,6 @@
schedule(fillFifoEvent, nextCycle());
}
-
-Tick
-Pl111::nextCycle()
-{
- Tick nextTick = curTick() + clock - 1;
- nextTick -= nextTick%clock;
- return nextTick;
-}
-
-Tick
-Pl111::nextCycle(Tick beginTick)
-{
- Tick nextTick = beginTick;
- if (nextTick%clock!=0)
- nextTick = nextTick - (nextTick%clock) + clock;
-
- assert(nextTick >= curTick());
- return nextTick;
-}
-
void
Pl111::serialize(std::ostream &os)
{
@@ -586,7 +566,6 @@
uint8_t clcdCrsrMis_serial = clcdCrsrMis;
SERIALIZE_SCALAR(clcdCrsrMis_serial);
- SERIALIZE_SCALAR(clock);
SERIALIZE_SCALAR(height);
SERIALIZE_SCALAR(width);
SERIALIZE_SCALAR(bytesPerPixel);
@@ -689,7 +668,6 @@
UNSERIALIZE_SCALAR(clcdCrsrMis_serial);
clcdCrsrMis = clcdCrsrMis_serial;
- UNSERIALIZE_SCALAR(clock);
UNSERIALIZE_SCALAR(height);
UNSERIALIZE_SCALAR(width);
UNSERIALIZE_SCALAR(bytesPerPixel);
diff -r 38dd0780322a -r e0bad9d7bbd6 src/dev/arm/pl111.hh
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