changeset d112473185ea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d112473185ea
description:
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
diffstat:
configs/common/FSConfig.py | 12 +-
configs/example/fs.py | 7 +-
src/mem/Bridge.py | 17 +-
src/mem/SConscript | 2 +-
src/mem/bridge.cc | 268 ++++++++++---------------
src/mem/bridge.hh | 138 ++++--------
tests/configs/twosys-tsunami-simple-atomic.py | 6 +-
7 files changed, 187 insertions(+), 263 deletions(-)
diffs (truncated from 904 to 300 lines):
diff -r 3b5e13ac1940 -r d112473185ea configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Wed Aug 22 11:39:56 2012 -0400
+++ b/configs/common/FSConfig.py Wed Aug 22 11:39:58 2012 -0400
@@ -71,7 +71,7 @@
self.membus = MemBus()
# By default the bridge responds to all addresses above the I/O
# base address (including the PCI config space)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns',
+ self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
self.bridge.master = self.iobus.slave
@@ -174,7 +174,7 @@
self.readfile = mdesc.script()
self.iobus = NoncoherentBus()
self.membus = MemBus()
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
@@ -240,7 +240,7 @@
self.iobus = NoncoherentBus()
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -322,7 +322,7 @@
self.readfile = mdesc.script()
self.iobus = NoncoherentBus()
self.membus = MemBus()
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.physmem = SimpleMemory(range = AddrRange('1GB'))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -368,7 +368,7 @@
# North Bridge
x86_sys.iobus = NoncoherentBus()
- x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
# Allow the bridge to pass through the IO APIC (two pages),
@@ -387,7 +387,7 @@
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
- x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.apicbridge = Bridge(delay='50ns')
x86_sys.apicbridge.slave = x86_sys.iobus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
diff -r 3b5e13ac1940 -r d112473185ea configs/example/fs.py
--- a/configs/example/fs.py Wed Aug 22 11:39:56 2012 -0400
+++ b/configs/example/fs.py Wed Aug 22 11:39:58 2012 -0400
@@ -126,8 +126,7 @@
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
- test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [test_sys.physmem.range])
+ test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range])
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
@@ -162,8 +161,8 @@
drive_sys.cpu.fastmem = True
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
- drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [drive_sys.physmem.range])
+ drive_sys.iobridge = Bridge(delay='50ns',
+ ranges = [drive_sys.physmem.range])
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
diff -r 3b5e13ac1940 -r d112473185ea src/mem/Bridge.py
--- a/src/mem/Bridge.py Wed Aug 22 11:39:56 2012 -0400
+++ b/src/mem/Bridge.py Wed Aug 22 11:39:58 2012 -0400
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -25,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
+# Andreas Hansson
from m5.params import *
from MemObject import MemObject
@@ -34,9 +47,7 @@
slave = SlavePort('Slave port')
master = MasterPort('Master port')
req_size = Param.Int(16, "The number of requests to buffer")
- resp_size = Param.Int(16, "The number of requests to buffer")
+ resp_size = Param.Int(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
- nack_delay = Param.Latency('0ns', "The latency of this bridge")
- write_ack = Param.Bool(False, "Should this bridge ack writes")
ranges = VectorParam.AddrRange([AllMemory],
"Address ranges to pass through the bridge")
diff -r 3b5e13ac1940 -r d112473185ea src/mem/SConscript
--- a/src/mem/SConscript Wed Aug 22 11:39:56 2012 -0400
+++ b/src/mem/SConscript Wed Aug 22 11:39:58 2012 -0400
@@ -65,7 +65,7 @@
CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
'NoncoherentBus'])
-DebugFlag('BusBridge')
+DebugFlag('Bridge')
DebugFlag('CommMonitor')
DebugFlag('LLSC')
DebugFlag('MMU')
diff -r 3b5e13ac1940 -r d112473185ea src/mem/bridge.cc
--- a/src/mem/bridge.cc Wed Aug 22 11:39:56 2012 -0400
+++ b/src/mem/bridge.cc Wed Aug 22 11:39:58 2012 -0400
@@ -49,43 +49,37 @@
*/
#include "base/trace.hh"
-#include "debug/BusBridge.hh"
+#include "debug/Bridge.hh"
#include "mem/bridge.hh"
#include "params/Bridge.hh"
-Bridge::BridgeSlavePort::BridgeSlavePort(const std::string &_name,
- Bridge* _bridge,
+Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
+ Bridge& _bridge,
BridgeMasterPort& _masterPort,
- int _delay, int _nack_delay,
- int _resp_limit,
+ int _delay, int _resp_limit,
std::vector<Range<Addr> > _ranges)
- : SlavePort(_name, _bridge), bridge(_bridge), masterPort(_masterPort),
- delay(_delay), nackDelay(_nack_delay),
- ranges(_ranges.begin(), _ranges.end()),
- outstandingResponses(0), inRetry(false),
+ : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
+ delay(_delay), ranges(_ranges.begin(), _ranges.end()),
+ outstandingResponses(0), retryReq(false),
respQueueLimit(_resp_limit), sendEvent(*this)
{
}
-Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name,
- Bridge* _bridge,
+Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
+ Bridge& _bridge,
BridgeSlavePort& _slavePort,
int _delay, int _req_limit)
- : MasterPort(_name, _bridge), bridge(_bridge), slavePort(_slavePort),
- delay(_delay), inRetry(false), reqQueueLimit(_req_limit),
- sendEvent(*this)
+ : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
+ delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
{
}
Bridge::Bridge(Params *p)
: MemObject(p),
- slavePort(p->name + ".slave", this, masterPort, p->delay,
- p->nack_delay, p->resp_size, p->ranges),
- masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size),
- ackWrites(p->write_ack), _params(p)
+ slavePort(p->name + ".slave", *this, masterPort, p->delay, p->resp_size,
+ p->ranges),
+ masterPort(p->name + ".master", *this, slavePort, p->delay, p->req_size)
{
- if (ackWrites)
- panic("No support for acknowledging writes\n");
}
MasterPort&
@@ -133,7 +127,7 @@
bool
Bridge::BridgeMasterPort::reqQueueFull()
{
- return requestQueue.size() == reqQueueLimit;
+ return transmitList.size() == reqQueueLimit;
}
bool
@@ -141,12 +135,12 @@
{
// all checks are done when the request is accepted on the slave
// side, so we are guaranteed to have space for the response
- DPRINTF(BusBridge, "recvTiming: response %s addr 0x%x\n",
+ DPRINTF(Bridge, "recvTimingResp: %s addr 0x%x\n",
pkt->cmdString(), pkt->getAddr());
- DPRINTF(BusBridge, "Request queue size: %d\n", requestQueue.size());
+ DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
- slavePort.queueForSendTiming(pkt);
+ slavePort.schedTimingResp(pkt, curTick() + delay);
return true;
}
@@ -154,95 +148,52 @@
bool
Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
{
- DPRINTF(BusBridge, "recvTiming: request %s addr 0x%x\n",
+ DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
pkt->cmdString(), pkt->getAddr());
- DPRINTF(BusBridge, "Response queue size: %d outresp: %d\n",
- responseQueue.size(), outstandingResponses);
+ // ensure we do not have something waiting to retry
+ if(retryReq)
+ return false;
+
+ DPRINTF(Bridge, "Response queue size: %d outresp: %d\n",
+ transmitList.size(), outstandingResponses);
if (masterPort.reqQueueFull()) {
- DPRINTF(BusBridge, "Request queue full, nacking\n");
- nackRequest(pkt);
- return true;
- }
-
- if (pkt->needsResponse()) {
+ DPRINTF(Bridge, "Request queue full\n");
+ retryReq = true;
+ } else if (pkt->needsResponse()) {
if (respQueueFull()) {
- DPRINTF(BusBridge,
- "Response queue full, no space for response, nacking\n");
- DPRINTF(BusBridge,
- "queue size: %d outstanding resp: %d\n",
- responseQueue.size(), outstandingResponses);
- nackRequest(pkt);
- return true;
+ DPRINTF(Bridge, "Response queue full\n");
+ retryReq = true;
} else {
- DPRINTF(BusBridge, "Request Needs response, reserving space\n");
+ DPRINTF(Bridge, "Reserving space for response\n");
assert(outstandingResponses != respQueueLimit);
++outstandingResponses;
+ retryReq = false;
+ masterPort.schedTimingReq(pkt, curTick() + delay);
}
}
- masterPort.queueForSendTiming(pkt);
-
- return true;
+ // remember that we are now stalling a packet and that we have to
+ // tell the sending master to retry once space becomes available,
+ // we make no distinction whether the stalling is due to the
+ // request queue or response queue being full
+ return !retryReq;
}
void
-Bridge::BridgeSlavePort::nackRequest(PacketPtr pkt)
+Bridge::BridgeSlavePort::retryStalledReq()
{
- // Nack the packet
- pkt->makeTimingResponse();
- pkt->setNacked();
-
- // The Nack packets are stored in the response queue just like any
- // other response, but they do not occupy any space as this is
- // tracked by the outstandingResponses, this guarantees space for
- // the Nack packets, but implicitly means we have an (unrealistic)
- // unbounded Nack queue.
-
- // put it on the list to send
- Tick readyTime = curTick() + nackDelay;
- DeferredResponse resp(pkt, readyTime, true);
-
- // nothing on the list, add it and we're done
- if (responseQueue.empty()) {
- assert(!sendEvent.scheduled());
- bridge->schedule(sendEvent, readyTime);
- responseQueue.push_back(resp);
- return;
+ if (retryReq) {
+ DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
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