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src/cpu/base.cc <http://reviews.gem5.org/r/1359/#comment3403> Actually, thinking about this, is this necessary? If I want to have the two sets of CPUs have their own caches/TLBs and maintain their connections even when switched out, this assert will fail. Whereas with the check for a connection, this code will assume the new CPU already has a cache, or something connected to it, and function properly. I guess it depends on what we want this functionality to do, if it's strictly for fast-forwarding then this is probably correct. - Anthony Gutierrez On Aug. 20, 2012, 7:34 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1359/ > ----------------------------------------------------------- > > (Updated Aug. 20, 2012, 7:34 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9157:e5872950c9a3 > --------------------------- > Port: Stricter port bind/unbind semantics > > This patch tightens up the semantics around port binding and checks > that the ports that are being bound are currently not connected, and > similarly connected before unbind is called. > > The patch consequently also changes the order of the unbind and bind > for the switching of CPUs to ensure that the rules are adhered > to. Previously the ports would be "over-written" without any check. > > There are no changes in behaviour due to this patch, and the only > place where the unbind functionality is used is in the CPU. > > > Diffs > ----- > > src/cpu/base.cc 4c67c26fa76e > src/mem/port.hh 4c67c26fa76e > src/mem/port.cc 4c67c26fa76e > > Diff: http://reviews.gem5.org/r/1359/diff/ > > > Testing > ------- > > Ran a simple se and fs simulation and created and restored from > checkpoints for both. > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
