changeset 8ee71266699b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8ee71266699b
description:
stats: Update Ruby regressions for memory controller fix
diffstat:
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
| 120 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 40 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
| 106 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 40 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
| 108 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
| 38 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
| 98 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
| 40 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
| 102 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 40 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
| 84 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 40 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
| 92 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
| 38 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
| 25 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
| 803 +++---
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
| 146 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
| 10 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
| 44 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
| 23 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
| 1042 +++++-----
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
| 146 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
| 10 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
| 42 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
| 23 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
| 1034 ++++----
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
| 146 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
| 44 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
| 53 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
| 450 ++--
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
| 146 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
| 10 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
| 44 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
| 8 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
| 380 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
| 10 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
| 12 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
| 8 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
| 366 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
| 10 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
| 12 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
| 8 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
| 344 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
| 12 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
| 8 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
| 196 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
| 10 +-
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
| 10 +-
64 files changed, 3479 insertions(+), 3302 deletions(-)
diffs (truncated from 12112 to 300 lines):
diff -r 43da8ae0f36e -r 8ee71266699b
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
---
a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
Wed Sep 05 20:51:41 2012 -0500
+++
b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
Wed Sep 05 20:53:34 2012 -0500
@@ -10,6 +10,7 @@
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -78,7 +78,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -119,9 +119,9 @@
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
+clock=3
dimm_bit_0=12
dimms_per_channel=2
-mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -130,6 +130,7 @@
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
+ruby_system=system.ruby
tFaw=0
version=0
@@ -183,6 +184,7 @@
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
+clock=1
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
@@ -227,6 +229,7 @@
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
@@ -351,6 +354,7 @@
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
+clock=1
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff -r 43da8ae0f36e -r 8ee71266699b
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
---
a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
Wed Sep 05 20:51:41 2012 -0500
+++
b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
Wed Sep 05 20:53:34 2012 -0500
@@ -1,26 +1,26 @@
-Real time: Jul/10/2012 17:30:50
+Real time: Sep/01/2012 14:02:52
Profiler Stats
--------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.62
-Virtual_time_in_minutes: 0.0103333
-Virtual_time_in_hours: 0.000172222
-Virtual_time_in_days: 7.17593e-06
+Virtual_time_in_seconds: 0.56
+Virtual_time_in_minutes: 0.00933333
+Virtual_time_in_hours: 0.000155556
+Virtual_time_in_days: 6.48148e-06
-Ruby_current_time: 279353
+Ruby_current_time: 138616
Ruby_start_time: 0
-Ruby_cycles: 279353
+Ruby_cycles: 138616
-mbytes_resident: 47.9336
-mbytes_total: 230.535
-resident_ratio: 0.20794
+mbytes_resident: 49.5195
+mbytes_total: 259.898
+resident_ratio: 0.190594
-ruby_cycles_executed: [ 279354 ]
+ruby_cycles_executed: [ 138617 ]
Busy Controller Counts:
L1Cache-0:0
@@ -30,15 +30,15 @@
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1
| standard deviation: 0 | 0 8465 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1
| standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard
deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21
12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1
0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard
deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard
deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 |
standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0
0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 |
standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28
22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 1 max: 113 count: 8448 average: 15.4081 | standard
deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0 1 0 2 1
0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 37.6915 | standard
deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
0 0 0 0 0 0 1 3 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 110 count: 865 average: 20.5237 | standard
deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 3 ]
+miss_latency_IFETCH: [binsize: 1 max: 98 count: 6400 average: 10.5978 |
standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0
1 ]
+miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 15.4081 |
standard deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0
1 0 2 1 0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0
average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average:
NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0
average: NaN |standard deviation: NaN | 0 ]
@@ -49,9 +49,9 @@
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0
average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0
average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 |
standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 |
standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0
0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 |
standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0
0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 37.6915 |
standard deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 1 3 0 0 1 ]
+miss_latency_ST_NULL: [binsize: 1 max: 110 count: 865 average: 20.5237 |
standard deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 3 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 98 count: 6400 average: 10.5978 |
standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0
1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -65,10 +65,10 @@
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 |
standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017
| standard deviation: 0.0240441 | 6919 0 1 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average:
0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0
0 0 1 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 2 count: 5879 average:
0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
+Total_delay_cycles: [binsize: 1 max: 4 count: 9645 average: 0.0609642 |
standard deviation: 0.490156 | 9498 0 0 0 147 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 |
standard deviation: 0 | 6920 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 2725 average:
0.21578 | standard deviation: 0.90398 | 2578 0 0 0 147 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 5879 average:
0 | standard deviation: 0 | 5879 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average:
0 | standard deviation: 0 | 1041 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN
|standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN
|standard deviation: NaN | 0 ]
@@ -83,11 +83,11 @@
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13465
-page_faults: 0
+page_reclaims: 10172
+page_faults: 15
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1112
+block_outputs: 80
Network Stats
-------------
@@ -102,9 +102,9 @@
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 1.87549
- links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 3.77969
+ links_utilized_percent_switch_0_link_0: 5.36987 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 2.1895 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0
0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0
0 0 0 0 0 ] base_latency: 1
@@ -116,9 +116,9 @@
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.64029
- links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 7.33627
+ links_utilized_percent_switch_1_link_0: 7.45296 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 7.21959 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0
0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0
0 0 0 0 0 ] base_latency: 1
@@ -132,9 +132,9 @@
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 1.76479
- links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 3.55659
+ links_utilized_percent_switch_2_link_0: 1.84971 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 5.26346 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0
0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0
0 0 0 ] base_latency: 1
@@ -144,10 +144,10 @@
switch_3_inlinks: 3
switch_3_outlinks: 3
-links_utilized_percent_switch_3: 2.42686
- links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 4.89085
+ links_utilized_percent_switch_3_link_0: 5.36987 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 7.45296 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 1.84971 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0
0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0
0 0 0 0 0 ] base_latency: 1
@@ -186,8 +186,8 @@
--- L1Cache ---
- Event Counts -
-Load [1185 ] 1185
-Ifetch [6414 ] 6414
+Load [1183 ] 1183
+Ifetch [6400 ] 6400
Store [865 ] 865
Inv [1041 ] 1041
L1_Replacement [1354 ] 1354
@@ -216,12 +216,12 @@
I L1_Replacement [556 ] 556
S Load [0 ] 0
-S Ifetch [5723 ] 5723
+S Ifetch [5709 ] 5709
S Store [0 ] 0
S Inv [325 ] 325
S L1_Replacement [362 ] 362
-E Load [454 ] 454
+E Load [452 ] 452
E Ifetch [0 ] 0
E Store [71 ] 71
E Inv [219 ] 219
@@ -307,7 +307,7 @@
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [691 ] 691
-L1_GETS [585 ] 585
+L1_GETS [583 ] 583
L1_GETX [216 ] 216
L1_UPGRADE [0 ] 0
L1_PUTX [436 ] 436
@@ -364,7 +364,7 @@
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
-M_I L1_GETS [2 ] 2
+M_I L1_GETS [0 ] 0
M_I L1_GETX [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
@@ -518,19 +518,19 @@
memory_total_requests: 1737
memory_reads: 1460
memory_writes: 277
- memory_refreshes: 582
- memory_total_request_delays: 821
- memory_delays_per_request: 0.472654
- memory_delays_in_input_queue: 84
+ memory_refreshes: 963
+ memory_total_request_delays: 341
+ memory_delays_per_request: 0.196315
+ memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 737
- memory_stalls_for_bank_busy: 197
+ memory_delays_stalled_at_head_of_bank_queue: 341
+ memory_stalls_for_bank_busy: 166
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 40
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
