changeset a1a8f137b796 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a1a8f137b796
description:
Param: Transition to Cycles for relevant parameters
This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.
An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.
diffstat:
src/base/types.hh | 3 ++
src/cpu/FuncUnit.py | 4 +-
src/cpu/func_unit.hh | 4 +-
src/cpu/inorder/InOrderCPU.py | 20 +++++++++---------
src/cpu/inorder/params.hh | 20 +++++++++---------
src/cpu/o3/O3CPU.py | 42 +++++++++++++++++++-------------------
src/cpu/o3/commit.hh | 14 ++++++------
src/cpu/o3/decode.hh | 16 +++++++-------
src/cpu/o3/fetch.hh | 16 +++++++-------
src/cpu/o3/fu_pool.cc | 6 ++--
src/cpu/o3/fu_pool.hh | 10 ++++----
src/cpu/o3/iew.hh | 12 +++++-----
src/cpu/o3/inst_queue.hh | 2 +-
src/cpu/o3/inst_queue_impl.hh | 8 +++---
src/mem/Bus.py | 2 +-
src/mem/cache/BaseCache.py | 2 +-
src/mem/cache/tags/iic.cc | 2 +
src/mem/cache/tags/iic.hh | 2 +-
src/mem/ruby/system/BankedArray.cc | 2 +-
src/mem/ruby/system/BankedArray.hh | 4 +-
src/mem/ruby/system/Cache.py | 4 +-
src/mem/ruby/system/Sequencer.hh | 2 +-
src/mem/ruby/system/Sequencer.py | 2 +-
src/python/m5/params.py | 12 ++++++++--
24 files changed, 111 insertions(+), 100 deletions(-)
diffs (truncated from 555 to 300 lines):
diff -r 8ee71266699b -r a1a8f137b796 src/base/types.hh
--- a/src/base/types.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/base/types.hh Fri Sep 07 12:34:38 2012 -0400
@@ -89,6 +89,9 @@
/** Explicit constructor assigning a value. */
explicit Cycles(uint64_t _c) : c(_c) { }
+ /** Default constructor for parameter classes. */
+ Cycles() : c(0) { }
+
#ifndef SWIG // keep the operators away from SWIG
/** Converting back to the value type. */
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/FuncUnit.py
--- a/src/cpu/FuncUnit.py Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/FuncUnit.py Fri Sep 07 12:34:38 2012 -0400
@@ -53,9 +53,9 @@
class OpDesc(SimObject):
type = 'OpDesc'
- issueLat = Param.Int(1, "cycles until another can be issued")
+ issueLat = Param.Cycles(1, "cycles until another can be issued")
opClass = Param.OpClass("type of operation")
- opLat = Param.Int(1, "cycles until result is available")
+ opLat = Param.Cycles(1, "cycles until result is available")
class FUDesc(SimObject):
type = 'FUDesc'
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/func_unit.hh
--- a/src/cpu/func_unit.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/func_unit.hh Fri Sep 07 12:34:38 2012 -0400
@@ -51,8 +51,8 @@
{
public:
OpClass opClass;
- unsigned opLat;
- unsigned issueLat;
+ Cycles opLat;
+ Cycles issueLat;
OpDesc(const OpDescParams *p)
: SimObject(p), opClass(p->opClass), opLat(p->opLat),
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/inorder/InOrderCPU.py Fri Sep 07 12:34:38 2012 -0400
@@ -65,13 +65,13 @@
stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
- multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
- multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
- div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations")
- div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide
Operations")
- div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations")
- div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide
Operations")
- div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations")
- div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide
Operations")
- div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations")
- div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide
Operations")
+ multLatency = Param.Cycles(1, "Latency for Multiply Operations")
+ multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations")
+ div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations")
+ div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations")
+ div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations")
+ div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide
Operations")
+ div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations")
+ div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide
Operations")
+ div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
+ div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide
Operations")
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/inorder/params.hh
--- a/src/cpu/inorder/params.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/inorder/params.hh Fri Sep 07 12:34:38 2012 -0400
@@ -97,24 +97,24 @@
// then MDU must be defined as its own SimObject so that an arbitrary # can
// be defined with different parameters
/** Latency & Repeat Rate for Multiply Insts */
- unsigned multLatency;
- unsigned multRepeatRate;
+ Cycles multLatency;
+ Cycles multRepeatRate;
/** Latency & Repeat Rate for 8-bit Divide Insts */
- unsigned div8Latency;
- unsigned div8RepeatRate;
+ Cycles div8Latency;
+ Cycles div8RepeatRate;
/** Latency & Repeat Rate for 16-bit Divide Insts */
- unsigned div16Latency;
- unsigned div16RepeatRate;
+ Cycles div16Latency;
+ Cycles div16RepeatRate;
/** Latency & Repeat Rate for 24-bit Divide Insts */
- unsigned div24Latency;
- unsigned div24RepeatRate;
+ Cycles div24Latency;
+ Cycles div24RepeatRate;
/** Latency & Repeat Rate for 32-bit Divide Insts */
- unsigned div32Latency;
- unsigned div32RepeatRate;
+ Cycles div32Latency;
+ Cycles div32RepeatRate;
};
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/O3CPU.py Fri Sep 07 12:34:38 2012 -0400
@@ -39,31 +39,31 @@
cachePorts = Param.Unsigned(200, "Cache Ports")
- decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
- renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
- iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
- "delay")
- commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
+ decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
+ renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
+ iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
+ "delay")
+ commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
fetchWidth = Param.Unsigned(8, "Fetch width")
- renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
- iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
- "delay")
- commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
- fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
+ renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
+ iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
+ "delay")
+ commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
+ fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
decodeWidth = Param.Unsigned(8, "Decode width")
- iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
- "delay")
- commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
- decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
+ iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
+ "delay")
+ commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
+ decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
renameWidth = Param.Unsigned(8, "Rename width")
- commitToIEWDelay = Param.Unsigned(1, "Commit to "
+ commitToIEWDelay = Param.Cycles(1, "Commit to "
"Issue/Execute/Writeback delay")
- renameToIEWDelay = Param.Unsigned(2, "Rename to "
+ renameToIEWDelay = Param.Cycles(2, "Rename to "
"Issue/Execute/Writeback delay")
- issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
+ issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
"to the IEW stage)")
dispatchWidth = Param.Unsigned(8, "Dispatch width")
issueWidth = Param.Unsigned(8, "Issue width")
@@ -71,13 +71,13 @@
wbDepth = Param.Unsigned(1, "Writeback depth")
fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
- iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
+ iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
"delay")
- renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
+ renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
commitWidth = Param.Unsigned(8, "Commit width")
squashWidth = Param.Unsigned(8, "Squash width")
- trapLatency = Param.Unsigned(13, "Trap latency")
- fetchTrapLatency = Param.Unsigned(1, "Fetch trap latency")
+ trapLatency = Param.Cycles(13, "Trap latency")
+ fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
backComSize = Param.Unsigned(5, "Time buffer size for backwards
communication")
forwardComSize = Param.Unsigned(5, "Time buffer size for forward
communication")
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/commit.hh Fri Sep 07 12:34:38 2012 -0400
@@ -375,16 +375,16 @@
/** Priority List used for Commit Policy */
std::list<ThreadID> priority_list;
- /** IEW to Commit delay, in ticks. */
- unsigned iewToCommitDelay;
+ /** IEW to Commit delay. */
+ Cycles iewToCommitDelay;
- /** Commit to IEW delay, in ticks. */
- unsigned commitToIEWDelay;
+ /** Commit to IEW delay. */
+ Cycles commitToIEWDelay;
- /** Rename to ROB delay, in ticks. */
- unsigned renameToROBDelay;
+ /** Rename to ROB delay. */
+ Cycles renameToROBDelay;
- unsigned fetchToCommitDelay;
+ Cycles fetchToCommitDelay;
/** Rename width, in instructions. Used so ROB knows how many
* instructions to get from the rename instruction queue.
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/decode.hh
--- a/src/cpu/o3/decode.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/decode.hh Fri Sep 07 12:34:38 2012 -0400
@@ -244,17 +244,17 @@
/** Tracks which stages are telling decode to stall. */
Stalls stalls[Impl::MaxThreads];
- /** Rename to decode delay, in ticks. */
- unsigned renameToDecodeDelay;
+ /** Rename to decode delay. */
+ Cycles renameToDecodeDelay;
- /** IEW to decode delay, in ticks. */
- unsigned iewToDecodeDelay;
+ /** IEW to decode delay. */
+ Cycles iewToDecodeDelay;
- /** Commit to decode delay, in ticks. */
- unsigned commitToDecodeDelay;
+ /** Commit to decode delay. */
+ Cycles commitToDecodeDelay;
- /** Fetch to decode delay, in ticks. */
- unsigned fetchToDecodeDelay;
+ /** Fetch to decode delay. */
+ Cycles fetchToDecodeDelay;
/** The width of decode, in instructions. */
unsigned decodeWidth;
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/fetch.hh Fri Sep 07 12:34:38 2012 -0400
@@ -428,17 +428,17 @@
/** Tracks which stages are telling fetch to stall. */
Stalls stalls[Impl::MaxThreads];
- /** Decode to fetch delay, in ticks. */
- unsigned decodeToFetchDelay;
+ /** Decode to fetch delay. */
+ Cycles decodeToFetchDelay;
- /** Rename to fetch delay, in ticks. */
- unsigned renameToFetchDelay;
+ /** Rename to fetch delay. */
+ Cycles renameToFetchDelay;
- /** IEW to fetch delay, in ticks. */
- unsigned iewToFetchDelay;
+ /** IEW to fetch delay. */
+ Cycles iewToFetchDelay;
- /** Commit to fetch delay, in ticks. */
- unsigned commitToFetchDelay;
+ /** Commit to fetch delay. */
+ Cycles commitToFetchDelay;
/** The width of fetch in instructions. */
unsigned fetchWidth;
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/fu_pool.cc
--- a/src/cpu/o3/fu_pool.cc Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/fu_pool.cc Fri Sep 07 12:34:38 2012 -0400
@@ -76,8 +76,8 @@
funcUnits.clear();
for (int i = 0; i < Num_OpClasses; ++i) {
- maxOpLatencies[i] = 0;
- maxIssueLatencies[i] = 0;
+ maxOpLatencies[i] = Cycles(0);
+ maxIssueLatencies[i] = Cycles(0);
}
//
@@ -149,7 +149,7 @@
}
void
-FUPool::annotateMemoryUnits(unsigned hit_latency)
+FUPool::annotateMemoryUnits(Cycles hit_latency)
{
maxOpLatencies[MemReadOp] = hit_latency;
diff -r 8ee71266699b -r a1a8f137b796 src/cpu/o3/fu_pool.hh
--- a/src/cpu/o3/fu_pool.hh Wed Sep 05 20:53:34 2012 -0500
+++ b/src/cpu/o3/fu_pool.hh Fri Sep 07 12:34:38 2012 -0400
@@ -59,9 +59,9 @@
{
private:
/** Maximum op execution latencies, per op class. */
- unsigned maxOpLatencies[Num_OpClasses];
+ Cycles maxOpLatencies[Num_OpClasses];
/** Maximum issue latencies, per op class. */
- unsigned maxIssueLatencies[Num_OpClasses];
+ Cycles maxIssueLatencies[Num_OpClasses];
/** Bitvector listing capabilities of this FU pool. */
std::bitset<Num_OpClasses> capabilityList;
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