changeset 3e5761bfa300 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3e5761bfa300
description:
ARM: Fix issue with with way MPIDR is read to include affinity levels.
The simple_bootloader checks for CPU0 in a manner incompatible with
systems
actually using affinity levels -- just looking at MPIDR[7:0]. However,
in
future we may wish to use real affinity levels and this method will be
in danger
of matching several CPUs with affinity0 = 0.
Match affinity2 == affinity1 == affinity0 == 0 instead.
diffstat:
system/arm/simple_bootloader/simple.S | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diffs (13 lines):
diff -r 64c434f26d58 -r 3e5761bfa300 system/arm/simple_bootloader/simple.S
--- a/system/arm/simple_bootloader/simple.S Fri Sep 07 14:20:53 2012 -0500
+++ b/system/arm/simple_bootloader/simple.S Fri Sep 07 14:20:53 2012 -0500
@@ -68,8 +68,7 @@
bootldr:
mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
- uxtb r8, r8 // isolate the lower 8 bits (affinity lvl 1)
- adds r8, r8, #0 // set flags for branch
+ bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels)
bxeq r3 // if it's 0 (CPU 0), branch to kernel
mov r8, #1
str r8, [r4, #0] // Enable CPU interface on GIC
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