changeset 2a5516167688 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a5516167688
description:
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 3020 +++++-----
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 1466 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1512 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2730 ++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1482 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1724 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
| 188 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 1884 +++---
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 900 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1760 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 932 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 1174 +-
12 files changed, 9403 insertions(+), 9369 deletions(-)
diffs (truncated from 20662 to 300 lines):
diff -r dd9d98c16121 -r 2a5516167688
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Sep 10 11:57:36 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Sep 10 11:57:37 2012 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.900530 #
Number of seconds simulated
-sim_ticks 1900530295500 #
Number of ticks simulated
-final_tick 1900530295500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.903503 #
Number of seconds simulated
+sim_ticks 1903503020500 #
Number of ticks simulated
+final_tick 1903503020500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 128893 #
Simulator instruction rate (inst/s)
-host_op_rate 128893 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4273489918 #
Simulator tick rate (ticks/s)
-host_mem_usage 307500 #
Number of bytes of host memory used
-host_seconds 444.73 #
Real time elapsed on the host
-sim_insts 57321882 #
Number of instructions simulated
-sim_ops 57321882 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 875200 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24658176 #
Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650816 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 108032 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 692736 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 28984960 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 875200 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 108032 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 983232 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7922432 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7922432 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13675 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 385284 #
Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41419 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1688 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10824 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 452890 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 123788 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 123788 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 460503 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12974366 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1394777 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 56843 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 364496 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15250986 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 460503 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 56843 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 517346 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4168538 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4168538 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4168538 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 460503 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12974366 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1394777 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 56843 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 364496 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19419523 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 345965 #
number of replacements
-system.l2c.tagsinuse 65264.028554 #
Cycle average of tags in use
-system.l2c.total_refs 2565305 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 411137 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 6.239538 #
Average number of references to valid blocks.
-system.l2c.warmup_cycle 6370050000 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53566.065326 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5313.128544 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6099.641645 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 209.824884 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 75.368156 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.817353 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.081072 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.093073 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.003202 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.001150 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.995850 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 778193 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 689575 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 314248 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 100958 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1882974 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 806039 #
number of Writeback hits
-system.l2c.Writeback_hits::total 806039 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 174 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 439 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 613 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 52 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 31 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 83 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 128167 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 44386 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 172553 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 778193 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 817742 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 314248 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 145344 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2055527 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 778193 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 817742 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 314248 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 145344 #
number of overall hits
-system.l2c.overall_hits::total 2055527 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13677 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 272973 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1705 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 853 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 289208 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2871 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1574 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 4445 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 724 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 747 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1471 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 113108 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 10072 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 123180 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13677 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 386081 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1705 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10925 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 412388 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13677 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 386081 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1705 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 10925 #
number of overall misses
-system.l2c.overall_misses::total 412388 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 728382998
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 14214430499
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 91270500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 46668499
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 15080752496 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 22402914 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3106500
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6061979997
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 549631499
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6611611496 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 728382998 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 20276410496 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 91270500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 596299998 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21692363992 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 728382998
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 20276410496
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 91270500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 596299998
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 21692363992 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 791870 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 962548 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 315953 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 101811 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2172182 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 806039 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 806039 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 3045 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 2013 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 5058 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 776
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 778
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1554 #
number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 241275 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 54458 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 295733 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 791870 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1203823 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 315953 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 156269 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2467915 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 791870 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1203823 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 315953 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 156269 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2467915 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.017272 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.283594 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.005396 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.008378 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.133142 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942857
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781918
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.878806 #
miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.932990
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.960154
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.946589 #
miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.468793 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.184950 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.416524 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.017272 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.320712 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.005396 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.069911 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.167100 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.017272 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.320712 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.005396 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.069911 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.167100 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52145.004620
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 900.034831
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 5040.025647
# average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3857.044199
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 2111.828688
# average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53674.391102
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515
# average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52601.831266 #
average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515
# average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52601.831266
# average overall miss latency
+host_inst_rate 196271 #
Simulator instruction rate (inst/s)
+host_op_rate 196271 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6657053225 #
Simulator tick rate (ticks/s)
+host_mem_usage 303260 #
Number of bytes of host memory used
+host_seconds 285.94 #
Real time elapsed on the host
+sim_insts 56121257 #
Number of instructions simulated
+sim_ops 56121257 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 882432 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24721216 #
Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2649664 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 100416 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 648960 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 29002688 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 882432 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 100416 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 982848 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7936064 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7936064 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13788 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386269 #
Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41401 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1569 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10140 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 453167 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124001 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 124001 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 463583 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12987222 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1391994 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 52753 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 340929 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15236481 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 463583 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 52753 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 516336 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4169189 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4169189 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4169189 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 463583 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12987222 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1391994 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 52753 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 340929 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19405670 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 346253 #
number of replacements
+system.l2c.tagsinuse 65331.229324 #
Cycle average of tags in use
+system.l2c.total_refs 2603754 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 411399 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 6.329024 #
Average number of references to valid blocks.
+system.l2c.warmup_cycle 6380524000 #
Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 53709.821247 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5286.136461 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 6105.466815 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 198.491400 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 31.313401 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.819547 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.080660 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.093162 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.003029 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.000478 #
Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.996875 #
Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 965065 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 779439 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 111820 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 39391 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 1895715 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 831921 #
number of Writeback hits
+system.l2c.Writeback_hits::total 831921 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 172 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 73 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 245 #
number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 28 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 28 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 56 #
number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 165704 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 16093 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 181797 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 965065 #
number of demand (read+write) hits
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