changeset 46c3a74952ec in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=46c3a74952ec
description:
x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since
it
is not being used any where in the implementation, it creates an
unnecessary
dependency. Hence, it is being moved to a separate register.
diffstat:
src/arch/x86/isa/microops/debug.isa | 2 +-
src/arch/x86/isa/microops/fpop.isa | 4 +-
src/arch/x86/isa/microops/regop.isa | 64 +++++++++++++++++++++++------------
src/arch/x86/isa/microops/seqop.isa | 4 +-
src/arch/x86/isa/microops/specop.isa | 2 +-
src/arch/x86/isa/operands.isa | 9 ++--
src/arch/x86/regs/misc.hh | 2 +-
src/arch/x86/x86_traits.hh | 2 +-
8 files changed, 54 insertions(+), 35 deletions(-)
diffs (truncated from 331 to 300 lines):
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/microops/debug.isa
--- a/src/arch/x86/isa/microops/debug.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/microops/debug.isa Tue Sep 11 09:25:43 2012 -0500
@@ -142,7 +142,7 @@
"func": func,
"func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "checkCondition(ccFlagBits | cfofBits | \
- ecfBit | ezfBit, cc)"})
+ dfBit | ecfBit | ezfBit, cc)"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
decoder_output += MicroDebugConstructor.subst(iop)
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/microops/fpop.isa Tue Sep 11 09:25:43 2012 -0500
@@ -215,8 +215,8 @@
spm, SetStatus, dataSize)
code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
- cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
- src2)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \
+ ecfBit | ezfBit, src2)"
class Xorfp(FpOp):
code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/microops/regop.isa Tue Sep 11 09:25:43 2012 -0500
@@ -438,9 +438,10 @@
flag_code = '''
//Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit;
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit, ext & ~mask,
- result, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
+ ext & ~mask, result, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
//If a logic microop wants to set these, it wants to set them to 0.
@@ -451,29 +452,32 @@
class FlagRegOp(RegOp):
abstract = True
flag_code = '''
- uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
- ezfBit, ext, result, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, ext, result, psrc1, op2);
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
class SubRegOp(RegOp):
abstract = True
flag_code = '''
- uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
- ezfBit, ext, result, psrc1, ~op2, true);
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, ext, result, psrc1,
+ ~op2, true);
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
class CondRegOp(RegOp):
abstract = True
- cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
- ext)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \
+ ezfBit, ext)"
cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
class RdRegOp(RegOp):
@@ -732,9 +736,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -774,9 +779,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -815,9 +821,10 @@
}
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -856,9 +863,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -901,9 +909,10 @@
}
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -943,9 +952,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -990,9 +1000,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1047,9 +1058,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1110,9 +1122,10 @@
cfofBits = cfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
- uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -1130,6 +1143,7 @@
cfofBits = newFlags & cfofMask;
ecfBit = newFlags & ECFBit;
ezfBit = newFlags & EZFBit;
+ dfBit = newFlags & DFBit;
ccFlagBits = newFlags & ccFlagMask;
'''
@@ -1140,6 +1154,7 @@
// Get only the user flags
ccFlagBits = newFlags & ccFlagMask;
+ dfBit = newFlags & DFBit;
cfofBits = newFlags & cfofMask;
ecfBit = 0;
ezfBit = 0;
@@ -1152,22 +1167,25 @@
code = 'DestReg = NRIP - CSBase;'
class Ruflags(RdRegOp):
- code = 'DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit;'
+ code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;'
class Rflags(RdRegOp):
code = '''
- DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit | nccFlagBits;
+ DestReg = ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit | nccFlagBits;
'''
class Ruflag(RegOp):
code = '''
- int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+ int flag = bits(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, imm8);
DestReg = merge(DestReg, flag, dataSize);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
big_code = '''
- int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+ int flag = bits(ccFlagBits | cfofBits | dfBit |
+ ecfBit | ezfBit, imm8);
DestReg = flag & mask(dataSize * 8);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
@@ -1180,7 +1198,7 @@
class Rflag(RegOp):
code = '''
MiscReg flagMask = 0x3F7FDD5;
- MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+ MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
@@ -1190,7 +1208,7 @@
big_code = '''
MiscReg flagMask = 0x3F7FDD5;
- MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+ MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/microops/seqop.isa
--- a/src/arch/x86/isa/microops/seqop.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/microops/seqop.isa Tue Sep 11 09:25:43 2012 -0500
@@ -172,7 +172,7 @@
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
{"code": "nuIP = target;",
"else_code": "nuIP = nuIP;",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
"cond_control_flag_init": "flags[IsCondControl] = true"})
exec_output += SeqOpExecute.subst(iop)
@@ -190,7 +190,7 @@
iop = InstObjParams("eret", "EretFlags", "SeqOpBase",
{"code": "", "else_code": "",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
"cond_control_flag_init": ""})
exec_output += SeqOpExecute.subst(iop)
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/microops/specop.isa
--- a/src/arch/x86/isa/microops/specop.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/microops/specop.isa Tue Sep 11 09:25:43 2012 -0500
@@ -181,7 +181,7 @@
iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
{"code": "",
- "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)"})
exec_output = MicroFaultExecute.subst(iop)
header_output = MicroFaultDeclare.subst(iop)
diff -r ea379b718ff4 -r 46c3a74952ec src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Sun Jun 03 10:59:04 2012 -0500
+++ b/src/arch/x86/isa/operands.isa Tue Sep 11 09:25:43 2012 -0500
@@ -120,12 +120,13 @@
# nccFlagBits version holds the rest.
'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
- 'ecfBit': intReg('INTREG_PSEUDO(2)', 62),
- 'ezfBit': intReg('INTREG_PSEUDO(3)', 63),
+ 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
+ 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
+ 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
# These register should needs to be more protected so that later
# instructions don't map their indexes with an old value.
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