Hi all,
Following the introduction of Cycles as a parameter type, it would be good to
get the cache latencies expressed in Cycles rather than absolute time (Ticks).
To get there, a first step is to ensure that the caches have an appropriate
clock period. My first stab at this was to change
BaseCPU::addPrivateSplitL1Caches and BaseCPU:: addTwoLevelCacheHierarchy to
pass on the clock from the CPU. The problem is that the CPU clock is often set
_after_ everything is connected, and thus the resolution has to be deferred.
I asked a while back and Steve suggested using something along the line of
Parent.clock(), but I am not sure exactly how to do this and some input would
be appreciated.
Here is a snippet of what I am trying to do:
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -198,6 +198,9 @@
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
+ # Pass on our clock to the l1 caches with deferred resolution
+ self.icache.clock = self.clock
+ self.dcache.clock = self.clock
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
Ideas are very much welcome. I would like to say, "use the parents clock upon
instantiation, and do not simply get the current value".
Thanks,
Andreas
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