changeset 65f927bda74d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=65f927bda74d
description:
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 2917 ++++-----
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 1462 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1384 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2906 +++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1362 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1662 ++--
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
| 228 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
| 1052 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 1018 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 168 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 144 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1108 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1027 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 322 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 1162 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
| 262 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 1096 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 1144 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
| 356 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 1062 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 1058 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 1550 ++--
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 884 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 562 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 1124 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
| 42 +-
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
| 2854 ++++----
27 files changed, 14963 insertions(+), 14953 deletions(-)
diffs (truncated from 34161 to 300 lines):
diff -r bbdca4088834 -r 65f927bda74d
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Sep 18 10:30:02 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Sep 18 10:30:04 2012 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.903503 #
Number of seconds simulated
-sim_ticks 1903503020500 #
Number of ticks simulated
-final_tick 1903503020500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.903548 #
Number of seconds simulated
+sim_ticks 1903548166500 #
Number of ticks simulated
+final_tick 1903548166500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 196271 #
Simulator instruction rate (inst/s)
-host_op_rate 196271 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6657053225 #
Simulator tick rate (ticks/s)
-host_mem_usage 303260 #
Number of bytes of host memory used
-host_seconds 285.94 #
Real time elapsed on the host
-sim_insts 56121257 #
Number of instructions simulated
-sim_ops 56121257 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 882432 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24721216 #
Number of bytes read from this memory
+host_inst_rate 123505 #
Simulator instruction rate (inst/s)
+host_op_rate 123505 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4187441182 #
Simulator tick rate (ticks/s)
+host_mem_usage 303204 #
Number of bytes of host memory used
+host_seconds 454.59 #
Real time elapsed on the host
+sim_insts 56143492 #
Number of instructions simulated
+sim_ops 56143492 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 879488 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24796480 #
Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2649664 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 100416 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 648960 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 29002688 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 882432 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 100416 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 982848 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7936064 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7936064 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13788 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386269 #
Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 101696 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 559552 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 28986880 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 879488 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 101696 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 981184 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7925376 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7925376 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13742 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 387445 #
Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41401 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1569 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10140 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 453167 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124001 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 124001 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 463583 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12987222 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1391994 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 52753 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 340929 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15236481 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 463583 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 52753 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 516336 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4169189 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4169189 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4169189 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 463583 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12987222 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1391994 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 52753 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 340929 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19405670 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 346253 #
number of replacements
-system.l2c.tagsinuse 65331.229324 #
Cycle average of tags in use
-system.l2c.total_refs 2603754 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 411399 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 6.329024 #
Average number of references to valid blocks.
-system.l2c.warmup_cycle 6380524000 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53709.821247 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5286.136461 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6105.466815 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 198.491400 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 31.313401 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.819547 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.080660 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.093162 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.003029 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000478 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996875 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 965065 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 779439 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 111820 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 39391 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1895715 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 831921 #
number of Writeback hits
-system.l2c.Writeback_hits::total 831921 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 172 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 73 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 245 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 28 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 28 #
number of SCUpgradeReq hits
+system.physmem.num_reads::cpu1.inst 1589 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8743 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 452920 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123834 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 123834 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 462026 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13026453 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1391961 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 53424 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 293952 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15227815 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 462026 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 53424 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 515450 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4163475 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4163475 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4163475 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 462026 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13026453 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1391961 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 53424 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 293952 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19391291 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 346033 #
number of replacements
+system.l2c.tagsinuse 65330.743124 #
Cycle average of tags in use
+system.l2c.total_refs 2608063 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 411178 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 6.342905 #
Average number of references to valid blocks.
+system.l2c.warmup_cycle 6380526000 #
Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 53708.225390 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5276.213951 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 6113.589929 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 198.792297 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 33.921558 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.819522 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.080509 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.093286 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.003033 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.000518 #
Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.996868 #
Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 970913 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 780748 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 107670 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 39067 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 1898398 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 832636 #
number of Writeback hits
+system.l2c.Writeback_hits::total 832636 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 184 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 54 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 238 #
number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 27 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 29 #
number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 56 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 165704 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 16093 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 181797 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 965065 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 945143 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 111820 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 55484 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2077512 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 965065 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 945143 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 111820 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 55484 #
number of overall hits
-system.l2c.overall_hits::total 2077512 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13790 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 273025 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1586 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 787 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 289188 #
number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu0.data 168538 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 13567 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 182105 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 970913 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 949286 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 107670 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 52634 #
number of demand (read+write) hits
+system.l2c.demand_hits::total 2080503 #
number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 970913 #
number of overall hits
+system.l2c.overall_hits::cpu0.data 949286 #
number of overall hits
+system.l2c.overall_hits::cpu1.inst 107670 #
number of overall hits
+system.l2c.overall_hits::cpu1.data 52634 #
number of overall hits
+system.l2c.overall_hits::total 2080503 #
number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 13744 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 272909 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1606 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 887 #
number of ReadReq misses
+system.l2c.ReadReq_misses::total 289146 #
number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2478 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 547 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3025 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 39 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 78 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 117 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 113756 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 9451 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 123207 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13790 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 386781 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1586 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10238 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 412395 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13790 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 386781 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1586 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 10238 #
number of overall misses
-system.l2c.overall_misses::total 412395 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 734208497
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 14217029000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 84954500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 43255499
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 15079447496 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 2117000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 2247500
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 4364500 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 418000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 626000
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6097259996
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 516851999
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6614111995 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 734208497 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 20314288996 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 84954500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 560107498 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21693559491 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 734208497
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 20314288996
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 84954500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 560107498
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 21693559491 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 978855 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1052464 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 113406 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 40178 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2184903 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 831921 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 831921 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2650 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 620 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3270 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 67
# number of SCUpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_misses::cpu1.data 531 #
number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3009 #
number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 43 #
number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 77 #
number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 120 #
number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 114968 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 7955 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 122923 #
number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 13744 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 387877 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1606 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 8842 #
number of demand (read+write) misses
+system.l2c.demand_misses::total 412069 #
number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 13744 #
number of overall misses
+system.l2c.overall_misses::cpu0.data 387877 #
number of overall misses
+system.l2c.overall_misses::cpu1.inst 1606 #
number of overall misses
+system.l2c.overall_misses::cpu1.data 8842 #
number of overall misses
+system.l2c.overall_misses::total 412069 #
number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 731783998
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 14210594000
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 85626000
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 48439997
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 15076443995 #
number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000
# number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500
# number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 3736500 #
number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000
# number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500
# number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 678500
# number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497
# number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 441967499
# number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 6632287996 #
number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 731783998 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 20400914497 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 85626000 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 490407496 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 21708731991 #
number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 731783998
# number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 20400914497
# number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 85626000
# number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 490407496
# number of overall miss cycles
+system.l2c.overall_miss_latency::total 21708731991 #
number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 984657 #
number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 1053657 #
number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 109276 #
number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 39954 #
number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2187544 #
number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 832636 #
number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 832636 #
number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 2662 #
number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 585 #
number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 3247 #
number of UpgradeReq accesses(hits+misses)
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