changeset dab0f29394f0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dab0f29394f0
description:
ARM: Predict target of more instructions that modify PC.
diffstat:
src/arch/arm/insts/macromem.cc | 8 ++++++++
src/arch/arm/isa/insts/data.isa | 15 ++++++++++-----
src/arch/arm/isa/templates/mem.isa | 18 ++++++++++++++++++
src/arch/arm/isa/templates/pred.isa | 9 +++++++++
4 files changed, 45 insertions(+), 5 deletions(-)
diffs (126 lines):
diff -r 1f43ff3d9bc6 -r dab0f29394f0 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc Tue Sep 25 11:49:40 2012 -0500
+++ b/src/arch/arm/insts/macromem.cc Tue Sep 25 11:49:40 2012 -0500
@@ -113,6 +113,14 @@
} else {
*++uop = new MicroLdrUop(machInst, regIdx,
INTREG_UREG0, up, addr);
+ if (reg == INTREG_PC) {
+ (*uop)->setFlag(StaticInst::IsControl);
+ if (!(condCode == COND_AL || condCode == COND_UC))
+ (*uop)->setFlag(StaticInst::IsCondControl);
+ else
+ (*uop)->setFlag(StaticInst::IsUncondControl);
+ (*uop)->setFlag(StaticInst::IsIndirectControl);
+ }
}
}
} else {
diff -r 1f43ff3d9bc6 -r dab0f29394f0 src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Tue Sep 25 11:49:40 2012 -0500
+++ b/src/arch/arm/isa/insts/data.isa Tue Sep 25 11:49:40 2012 -0500
@@ -116,7 +116,8 @@
regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
- buildCc = True, buildNonCc = True, instFlags = []):
+ buildCc = True, buildNonCc = True, isBranch = "0", \
+ instFlags = []):
cCode = carryCode[flagType]
vCode = overflowCode[flagType]
negBit = 31
@@ -133,10 +134,12 @@
immCode = secondOpRe.sub(immOp2, code)
immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
{"code" : immCode,
+ "is_branch" : isBranch,
"predicate_test": pickPredicate(immCode)}, instFlags)
immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
"DataImmOp",
{"code" : immCode + immCcCode,
+ "is_branch" : isBranch,
"predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)
def subst(iop):
@@ -244,7 +247,7 @@
if regRegAiw:
regRegCode = "AIW" + regRegCode
- buildImmDataInst(mnem, instCode, flagType)
+ buildImmDataInst(mnem, instCode, flagType, isBranch = isBranch)
buildRegDataInst(mnem, instCode, flagType,
isRasPop = isRasPop, isBranch = isBranch)
buildRegRegDataInst(mnem, regRegCode, flagType)
@@ -276,13 +279,15 @@
buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
- buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
+ buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub",
+ isBranch = "dest == INTREG_PC")
buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
- buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
+ buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add",
+ isBranch = "dest == INTREG_PC")
buildImmDataInst("adr", '''
Dest = resTemp = (PC & ~0x3) +
(op1 ? secondOp : -secondOp);
- ''')
+ ''', isBranch = "dest == INTREG_PC")
buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC,
"sub")
buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC,
"rsb")
diff -r 1f43ff3d9bc6 -r dab0f29394f0 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Tue Sep 25 11:49:40 2012 -0500
+++ b/src/arch/arm/isa/templates/mem.isa Tue Sep 25 11:49:40 2012 -0500
@@ -1155,6 +1155,15 @@
uops[1]->setLastMicroop();
}
+#else
+ if (_dest == INTREG_PC) {
+ flags[IsControl] = true;
+ flags[IsIndirectControl] = true;
+ if (conditional)
+ flags[IsCondControl] = true;
+ else
+ flags[IsUncondControl] = true;
+ }
#endif
}
}};
@@ -1198,6 +1207,15 @@
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
}
+#else
+ if (_dest == INTREG_PC) {
+ flags[IsControl] = true;
+ flags[IsIndirectControl] = true;
+ if (conditional)
+ flags[IsCondControl] = true;
+ else
+ flags[IsUncondControl] = true;
+ }
#endif
}
}};
diff -r 1f43ff3d9bc6 -r dab0f29394f0 src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa Tue Sep 25 11:49:40 2012 -0500
+++ b/src/arch/arm/isa/templates/pred.isa Tue Sep 25 11:49:40 2012 -0500
@@ -76,6 +76,15 @@
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
}
+
+ if (%(is_branch)s){
+ flags[IsControl] = true;
+ flags[IsIndirectControl] = true;
+ if (condCode == COND_AL || condCode == COND_UC)
+ flags[IsUncondControl] = true;
+ else
+ flags[IsCondControl] = true;
+ }
}
}};
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