changeset 5d0fcec59036 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5d0fcec59036
description:
ARM: Inst writing to cntrlReg registers not set as control inst
Deletion of the fact that instructions that writes to registers of type
"cntrlReg" are not set as control instruction (flag IsControl not set).
diffstat:
src/arch/arm/isa/operands.isa | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r dab0f29394f0 -r 5d0fcec59036 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Tue Sep 25 11:49:40 2012 -0500
+++ b/src/arch/arm/isa/operands.isa Tue Sep 25 11:49:40 2012 -0500
@@ -118,7 +118,7 @@
return ('IntReg', 'uw', idx, None, srtNormal)
def cntrlReg(idx, id = srtNormal, type = 'uw'):
- return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
+ return ('ControlReg', type, idx, None, id)
def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
return ('ControlReg', type, idx, None, id)
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