changeset 066099902102 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=066099902102
description:
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This
patch lets
a configurable response latency be set of the cache for the backward
path.
diffstat:
configs/common/Caches.py | 12 ++++++++----
configs/common/O3_ARM_v7a.py | 12 ++++++++----
src/mem/cache/BaseCache.py | 4 +++-
src/mem/cache/base.cc | 3 ++-
src/mem/cache/base.hh | 10 +++++++++-
src/mem/cache/builder.cc | 6 +++---
src/mem/cache/cache_impl.hh | 16 ++++++++++++----
tests/configs/inorder-timing.py | 6 ++++--
tests/configs/memtest.py | 6 ++++--
tests/configs/o3-timing-checker.py | 3 ++-
tests/configs/o3-timing-mp.py | 6 ++++--
tests/configs/o3-timing.py | 3 ++-
tests/configs/pc-o3-timing.py | 12 ++++++++----
tests/configs/pc-simple-atomic.py | 12 ++++++++----
tests/configs/pc-simple-timing.py | 12 ++++++++----
tests/configs/realview-o3-checker.py | 9 ++++++---
tests/configs/realview-o3-dual.py | 9 ++++++---
tests/configs/realview-o3.py | 9 ++++++---
tests/configs/realview-simple-atomic-dual.py | 9 ++++++---
tests/configs/realview-simple-atomic.py | 9 ++++++---
tests/configs/realview-simple-timing-dual.py | 9 ++++++---
tests/configs/realview-simple-timing.py | 9 ++++++---
tests/configs/simple-atomic-mp.py | 6 ++++--
tests/configs/simple-timing-mp.py | 6 ++++--
tests/configs/simple-timing.py | 5 +++--
tests/configs/tsunami-inorder.py | 9 ++++++---
tests/configs/tsunami-o3-dual.py | 9 ++++++---
tests/configs/tsunami-o3.py | 9 ++++++---
tests/configs/tsunami-simple-atomic-dual.py | 9 ++++++---
tests/configs/tsunami-simple-atomic.py | 9 ++++++---
tests/configs/tsunami-simple-timing-dual.py | 9 ++++++---
tests/configs/tsunami-simple-timing.py | 9 ++++++---
32 files changed, 180 insertions(+), 86 deletions(-)
diffs (truncated from 952 to 300 lines):
diff -r 547845010c08 -r 066099902102 configs/common/Caches.py
--- a/configs/common/Caches.py Tue Sep 25 11:49:41 2012 -0500
+++ b/configs/common/Caches.py Tue Sep 25 11:49:41 2012 -0500
@@ -31,7 +31,8 @@
class L1Cache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 20
is_top_level = True
@@ -39,14 +40,16 @@
class L2Cache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
@@ -55,7 +58,8 @@
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
diff -r 547845010c08 -r 066099902102 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py Tue Sep 25 11:49:41 2012 -0500
+++ b/configs/common/O3_ARM_v7a.py Tue Sep 25 11:49:41 2012 -0500
@@ -147,7 +147,8 @@
# Instruction Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be
faster
class O3_ARM_v7a_ICache(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 2
tgts_per_mshr = 8
@@ -158,7 +159,8 @@
# Data Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be
faster
class O3_ARM_v7a_DCache(BaseCache):
- latency = '2ns'
+ hit_latency = '2ns'
+ response_latency = '2ns'
block_size = 64
mshrs = 6
tgts_per_mshr = 8
@@ -170,7 +172,8 @@
# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache):
- latency = '4ns'
+ hit_latency = '4ns'
+ response_latency = '4ns'
block_size = 64
mshrs = 6
tgts_per_mshr = 8
@@ -183,7 +186,8 @@
# L2 Cache
# All latencys assume a 1GHz clock rate, with a faster clock they would be
faster
class O3_ARM_v7aL2(BaseCache):
- latency = '12ns'
+ hit_latency = '12ns'
+ response_latency = '12ns'
block_size = 64
mshrs = 16
tgts_per_mshr = 8
diff -r 547845010c08 -r 066099902102 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Tue Sep 25 11:49:41 2012 -0500
+++ b/src/mem/cache/BaseCache.py Tue Sep 25 11:49:41 2012 -0500
@@ -36,7 +36,9 @@
type = 'BaseCache'
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Latency("Latency")
+ hit_latency = Param.Latency("The hit latency for this cache")
+ response_latency = Param.Latency(
+ "Additional cache latency for the return path to core on a miss");
hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
diff -r 547845010c08 -r 066099902102 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue Sep 25 11:49:41 2012 -0500
+++ b/src/mem/cache/base.cc Tue Sep 25 11:49:41 2012 -0500
@@ -69,7 +69,8 @@
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
MSHRQueue_WriteBuffer),
blkSize(p->block_size),
- hitLatency(p->latency),
+ hitLatency(p->hit_latency),
+ responseLatency(p->response_latency),
numTarget(p->tgts_per_mshr),
forwardSnoops(p->forward_snoops),
isTopLevel(p->is_top_level),
diff -r 547845010c08 -r 066099902102 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Tue Sep 25 11:49:41 2012 -0500
+++ b/src/mem/cache/base.hh Tue Sep 25 11:49:41 2012 -0500
@@ -229,7 +229,15 @@
/**
* The latency of a hit in this device.
*/
- int hitLatency;
+ const Tick hitLatency;
+
+ /**
+ * The latency of sending reponse to its upper level cache/core on a
+ * linefill. In most contemporary processors, the return path on a cache
+ * miss is much quicker that the hit latency. The responseLatency parameter
+ * tries to capture this latency.
+ */
+ const Tick responseLatency;
/** The number of targets for each MSHR. */
const int numTarget;
diff -r 547845010c08 -r 066099902102 src/mem/cache/builder.cc
--- a/src/mem/cache/builder.cc Tue Sep 25 11:49:41 2012 -0500
+++ b/src/mem/cache/builder.cc Tue Sep 25 11:49:41 2012 -0500
@@ -71,7 +71,7 @@
#if defined(USE_CACHE_FALRU)
#define BUILD_FALRU_CACHE do { \
- FALRU *tags = new FALRU(block_size, size, latency); \
+ FALRU *tags = new FALRU(block_size, size, hit_latency); \
BUILD_CACHE(FALRU, tags); \
} while (0)
#else
@@ -80,7 +80,7 @@
#if defined(USE_CACHE_LRU)
#define BUILD_LRU_CACHE do { \
- LRU *tags = new LRU(numSets, block_size, assoc, latency); \
+ LRU *tags = new LRU(numSets, block_size, assoc, hit_latency); \
BUILD_CACHE(LRU, tags); \
} while (0)
#else
@@ -124,7 +124,7 @@
iic_params.blkSize = block_size;
iic_params.assoc = assoc;
iic_params.hashDelay = hash_delay;
- iic_params.hitLatency = latency;
+ iic_params.hitLatency = hit_latency;
iic_params.rp = repl;
iic_params.subblockSize = subblock_size;
#else
diff -r 547845010c08 -r 066099902102 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Sep 25 11:49:41 2012 -0500
+++ b/src/mem/cache/cache_impl.hh Tue Sep 25 11:49:41 2012 -0500
@@ -897,8 +897,11 @@
transfer_offset += blkSize;
}
- // If critical word (no offset) return first word time
- completion_time = tags->getHitLatency() +
+ // If critical word (no offset) return first word time.
+ // responseLatency is the latency of the return path
+ // from lower level caches/memory to an upper level cache or
+ // the core.
+ completion_time = responseLatency +
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable());
@@ -911,11 +914,16 @@
assert(target->pkt->cmd == MemCmd::StoreCondReq ||
target->pkt->cmd == MemCmd::StoreCondFailReq ||
target->pkt->cmd == MemCmd::SCUpgradeFailReq);
- completion_time = tags->getHitLatency() + pkt->finishTime;
+ // responseLatency is the latency of the return path
+ // from lower level caches/memory to an upper level cache or
+ // the core.
+ completion_time = responseLatency + pkt->finishTime;
target->pkt->req->setExtraData(0);
} else {
// not a cache fill, just forwarding response
- completion_time = tags->getHitLatency() + pkt->finishTime;
+ // responseLatency is the latency of the return path
+ // from lower level cahces/memory to the core.
+ completion_time = responseLatency + pkt->finishTime;
if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getPtr<uint8_t>());
}
diff -r 547845010c08 -r 066099902102 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/inorder-timing.py Tue Sep 25 11:49:41 2012 -0500
@@ -33,7 +33,8 @@
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
@@ -43,7 +44,8 @@
cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', latency='10ns'))
+ MyCache(size = '2MB', hit_latency='10ns',
+ response_latency='10ns'))
cpu.clock = '2GHz'
diff -r 547845010c08 -r 066099902102 tests/configs/memtest.py
--- a/tests/configs/memtest.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/memtest.py Tue Sep 25 11:49:41 2012 -0500
@@ -34,7 +34,8 @@
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 12
tgts_per_mshr = 8
@@ -46,7 +47,8 @@
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff -r 547845010c08 -r 066099902102 tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/o3-timing-checker.py Tue Sep 25 11:49:41 2012 -0500
@@ -42,7 +42,8 @@
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
diff -r 547845010c08 -r 066099902102 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/o3-timing-mp.py Tue Sep 25 11:49:41 2012 -0500
@@ -35,7 +35,8 @@
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
@@ -47,7 +48,8 @@
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff -r 547845010c08 -r 066099902102 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/o3-timing.py Tue Sep 25 11:49:41 2012 -0500
@@ -33,7 +33,8 @@
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
diff -r 547845010c08 -r 066099902102 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Tue Sep 25 11:49:41 2012 -0500
+++ b/tests/configs/pc-o3-timing.py Tue Sep 25 11:49:41 2012 -0500
@@ -39,7 +39,8 @@
# ====================
class L1(BaseCache):
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