-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1450/
-----------------------------------------------------------
Review request for Default.
Description
-------
changesets:
9272:53a03371470f "Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.
The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.
The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache."
Diffs
-----
tests/configs/pc-o3-timing.py f8c85a7d109f
tests/configs/pc-simple-atomic.py f8c85a7d109f
tests/configs/pc-simple-timing.py f8c85a7d109f
tests/configs/realview-o3-checker.py f8c85a7d109f
tests/configs/realview-o3.py f8c85a7d109f
tests/configs/realview-simple-atomic.py f8c85a7d109f
tests/configs/realview-simple-timing.py f8c85a7d109f
tests/configs/tsunami-inorder.py f8c85a7d109f
tests/configs/tsunami-o3.py f8c85a7d109f
tests/configs/tsunami-simple-atomic.py f8c85a7d109f
tests/configs/tsunami-simple-timing.py f8c85a7d109f
Diff: http://reviews.gem5.org/r/1450/diff/
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas Hansson
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
