changeset 9901180cd573 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9901180cd573
description:
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
1560 ++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt |
1662 ++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1752 ++++----
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt |
1770 +++++-----
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt |
554 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
1132 +++---
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt |
188 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt |
1098 +++---
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt |
236 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
1034 ++--
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt |
244 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt |
999 ++--
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt |
236 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt |
1118 +++---
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt |
182 +-
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt |
198 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt |
1014 ++--
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt |
212 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt |
1166 +++---
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt |
278 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt |
1140 +++---
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt |
270 +-
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt |
534 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
1036 ++--
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt |
180 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt |
1032 ++--
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt |
176 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
1108 +++---
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt |
186 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
1208 +++---
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt |
234 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt |
698 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
1156 +++---
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt |
276 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt |
1226 +++---
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt |
276 +-
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt |
278 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt |
664 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |
1130 +++---
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt |
278 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
1171 +++---
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt |
278 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt |
278 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt |
522 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
1022 ++--
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt |
170 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt |
1040 ++--
tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt |
142 +-
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt |
128 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt |
1060 ++--
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt |
192 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt |
968 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt |
1008 ++--
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt |
1212 +++---
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt |
286 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt |
918 ++--
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt |
120 +-
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
800 ++--
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt |
120 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt |
980 ++--
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt |
980 ++--
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt |
120 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt |
362 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt |
746 ++--
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt |
120 +-
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt |
884 ++--
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt |
366 +-
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt |
120 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt |
922 ++--
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt |
120 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
1184 +++---
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt |
308 +-
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
874 ++--
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt |
120 +-
74 files changed, 24664 insertions(+), 24696 deletions(-)
diffs (truncated from 58283 to 300 lines):
diff -r f4ff625eae56 -r 9901180cd573
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Mon Oct
15 08:08:08 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Mon Oct
15 08:09:54 2012 -0400
@@ -1,244 +1,52 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.867374 #
Number of seconds simulated
-sim_ticks 1867373908500 #
Number of ticks simulated
-final_tick 1867373908500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.855236 #
Number of seconds simulated
+sim_ticks 1855236450500 #
Number of ticks simulated
+final_tick 1855236450500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 123272 #
Simulator instruction rate (inst/s)
-host_op_rate 123272 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4349339718 #
Simulator tick rate (ticks/s)
-host_mem_usage 299108 #
Number of bytes of host memory used
-host_seconds 429.35 #
Real time elapsed on the host
-sim_insts 52926469 #
Number of instructions simulated
-sim_ops 52926469 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 969792 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24879488 #
Number of bytes read from this memory
+host_inst_rate 87142 #
Simulator instruction rate (inst/s)
+host_op_rate 87142 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3050446700 #
Simulator tick rate (ticks/s)
+host_mem_usage 299400 #
Number of bytes of host memory used
+host_seconds 608.19 #
Real time elapsed on the host
+sim_insts 52998368 #
Number of instructions simulated
+sim_ops 52998368 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 969536 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24881216 #
Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 28501568 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 969792 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 969792 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7518720 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7518720 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15153 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388742 #
Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28503040 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 969536 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 969536 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7522688 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7522688 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15149 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388769 #
Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 445337 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117480 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 117480 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 519335 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13323249 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1420330 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15262914 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 519335 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 519335 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4026360 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4026360 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4026360 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 519335 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13323249 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1420330 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19289275 #
Total bandwidth to/from this memory (bytes/s)
-system.cpu.l2cache.replacements 338398
# number of replacements
-system.cpu.l2cache.tagsinuse 65348.140689
# Cycle average of tags in use
-system.cpu.l2cache.total_refs 2559915
# Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 403567
# Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 6.343222
# Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 4870006000
# Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 53844.889123
# Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417
# Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6139.525149
# Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.821608
# Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.081844
# Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.093682
# Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997133
# Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783
# number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 827771
# number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1835554
# number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 841020
# number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 841020
# number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 31
# number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 31
# number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3
# number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 3
# number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 185546
# number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 185546
# number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 1007783
# number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1013317
# number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2021100
# number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 1007783
# number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1013317
# number of overall hits
-system.cpu.l2cache.overall_hits::total 2021100
# number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 15155
# number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 273854
# number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 289009
# number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 54
# number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 54
# number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2
# number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2
# number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 115395
# number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 115395
# number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 15155
# number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 389249
# number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404404
# number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 15155
# number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 389249
# number of overall misses
-system.cpu.l2cache.overall_misses::total 404404
# number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998
# number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500
# number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 15066892498
# number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500
# number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 376500
# number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497
# number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497
# number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998
# number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997
# number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 21292255995
# number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998
# number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997
# number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 21292255995
# number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938
# number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625
# number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2124563
# number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 841020
# number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 841020
# number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85
# number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 85
# number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5
# number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 5
# number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941
# number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 300941
# number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1022938
# number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1402566
# number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2425504
# number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1022938
# number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1402566
# number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2425504
# number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815
# miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591
# miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.136032
# miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294
# miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294
# miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000
# miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000
# miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447
# miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447
# miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815
# miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526
# miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.166730
# miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815
# miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526
# miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.166730
# miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467
# average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172
# average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600
# average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222
# average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222
# average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961
# average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961
# average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467
# average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962
# average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995
# average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467
# average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962
# average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995
# average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0
# number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0
# number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0
# number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0
# number of fast writes performed
-system.cpu.l2cache.cache_copies 0
# number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 75968
# number of writebacks
-system.cpu.l2cache.writebacks::total 75968
# number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1
# number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 1
# number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1
# number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 1
# number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1
# number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 1
# number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154
# number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854
# number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 289008
# number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54
# number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 54
# number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2
# number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2
# number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395
# number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 115395
# number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154
# number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 389249
# number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 404403
# number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154
# number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 389249
# number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 404403
# number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998
# number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500
# number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498
# number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000
# number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000
# number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000
# number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000
# number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497
# number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497
# number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998
# number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997
# number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995
# number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998
# number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997
# number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995
# number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500
# number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500
# number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500
# number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500
# number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000
# number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000
# number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814
# mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591
# mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032
# mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294
# mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294
# mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000
# mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000
# mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447
# mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447
# mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814
# mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526
# mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729
# mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814
# mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526
# mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729
# mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472
# average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645
# average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960
# average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074
# average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074
# average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000
# average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000
# average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539
# average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539
# average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472
# average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277
# average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343
# average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472
# average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277
# average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343
# average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf
# average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf
# average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data
inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
# average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf
# average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf
# average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses 0
# Number of misses that were no-allocate
+system.physmem.num_reads::total 445360 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117542 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 117542 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 522594 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13411345 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1429623 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15363562 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 522594 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 522594 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4054841 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4054841 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4054841 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 522594 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13411345 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1429623 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19418402 #
Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 41685 #
number of replacements
-system.iocache.tagsinuse 1.309507 #
Cycle average of tags in use
+system.iocache.tagsinuse 1.255779 #
Cycle average of tags in use
system.iocache.total_refs 0 #
Total number of references to valid blocks.
system.iocache.sampled_refs 41701 #
Sample count of references to valid blocks.
system.iocache.avg_refs 0 #
Average number of references to valid blocks.
-system.iocache.warmup_cycle 1711308479000 #
Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.309507 #
Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.081844 #
Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.081844 #
Average percentage of cache occupancy
+system.iocache.warmup_cycle 1706412007000 #
Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.255779 #
Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.078486 #
Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.078486 #
Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173
# number of ReadReq misses
system.iocache.ReadReq_misses::total 173 #
number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552
# number of WriteReq misses
@@ -249,12 +57,12 @@
system.iocache.overall_misses::total 41725 #
number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20672998
# number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20672998
# number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806
# number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 11464497806
# number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 11485170804
# number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 11485170804 #
number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 11485170804
# number of overall miss cycles
-system.iocache.overall_miss_latency::total 11485170804
# number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806
# number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 11469598806
# number of WriteReq miss cycles
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