changeset a31a1243a3ed in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a31a1243a3ed
description:
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 3002 +++---
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 232 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1360 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2928 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1338 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1654 ++--
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
| 131 -
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
| 26 +-
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
| 70 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 70 +-
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 14 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 14 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 20 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 212 +-
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
| 18 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 18 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
| 14 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 22 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 14 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
| 18 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 22 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 14 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
| 26 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 1054 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 1076 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
| 18 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 18 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 940 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 452 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 2016 ++--
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 70 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1880 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 370 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 512 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 162 +-
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
| 14 +-
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
| 18 +-
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
| 18 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 14 +-
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
| 18 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 3847 ++++-----
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 1925 ++--
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
| 2842 +++---
44 files changed, 14176 insertions(+), 14339 deletions(-)
diffs (truncated from 32755 to 300 lines):
diff -r 3d6da8559605 -r a31a1243a3ed
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Oct 15 08:10:54 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Oct 15 08:12:21 2012 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.903548 #
Number of seconds simulated
-sim_ticks 1903548166500 #
Number of ticks simulated
-final_tick 1903548166500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 1.902683 #
Number of seconds simulated
+sim_ticks 1902682770000 #
Number of ticks simulated
+final_tick 1902682770000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 123505 #
Simulator instruction rate (inst/s)
-host_op_rate 123505 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4187441182 #
Simulator tick rate (ticks/s)
-host_mem_usage 303204 #
Number of bytes of host memory used
-host_seconds 454.59 #
Real time elapsed on the host
-sim_insts 56143492 #
Number of instructions simulated
-sim_ops 56143492 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 879488 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24796480 #
Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2649664 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 101696 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 559552 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 28986880 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 879488 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 101696 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 981184 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7925376 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 7925376 #
Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13742 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 387445 #
Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41401 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1589 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8743 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 452920 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 123834 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 123834 #
Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 462026 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13026453 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1391961 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 53424 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 293952 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15227815 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 462026 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 53424 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 515450 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4163475 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4163475 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4163475 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 462026 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13026453 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1391961 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 53424 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 293952 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19391291 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 346033 #
number of replacements
-system.l2c.tagsinuse 65330.743124 #
Cycle average of tags in use
-system.l2c.total_refs 2608063 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 411178 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 6.342905 #
Average number of references to valid blocks.
-system.l2c.warmup_cycle 6380526000 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53708.225390 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5276.213951 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6113.589929 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 198.792297 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 33.921558 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.819522 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.080509 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.093286 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.003033 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000518 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996868 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 970913 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 780748 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 107670 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 39067 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1898398 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 832636 #
number of Writeback hits
-system.l2c.Writeback_hits::total 832636 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 184 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 54 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 238 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 27 #
number of SCUpgradeReq hits
+host_inst_rate 192931 #
Simulator instruction rate (inst/s)
+host_op_rate 192931 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6436506827 #
Simulator tick rate (ticks/s)
+host_mem_usage 296908 #
Number of bytes of host memory used
+host_seconds 295.61 #
Real time elapsed on the host
+sim_insts 57032045 #
Number of instructions simulated
+sim_ops 57032045 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 906816 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24518592 #
Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650816 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 73984 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 789824 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 28940032 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 906816 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 73984 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 980800 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7895360 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 7895360 #
Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14169 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 383103 #
Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41419 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1156 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 12341 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 452188 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123365 #
Number of write requests responded to by this memory
+system.physmem.num_writes::total 123365 #
Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 476599 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12886327 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1393199 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 38884 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 415111 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15210119 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 476599 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 38884 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 515483 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4149593 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4149593 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4149593 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 476599 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12886327 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1393199 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 38884 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 415111 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19359713 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 345291 #
number of replacements
+system.l2c.tagsinuse 65280.360301 #
Cycle average of tags in use
+system.l2c.total_refs 2575351 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 410382 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 6.275497 #
Average number of references to valid blocks.
+system.l2c.warmup_cycle 6143524000 #
Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 53635.672684 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5378.326569 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 6042.958234 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 144.667579 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 78.735234 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.818415 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.082067 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.092208 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.002207 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001201 #
Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.996099 #
Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 798441 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 696934 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 292090 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 99595 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 1887060 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 812223 #
number of Writeback hits
+system.l2c.Writeback_hits::total 812223 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 169 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 397 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 566 #
number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 46 #
number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 29 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 56 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 168538 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 13567 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 182105 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 970913 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 949286 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 107670 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 52634 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2080503 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 970913 #
number of overall hits
-system.l2c.overall_hits::cpu0.data 949286 #
number of overall hits
-system.l2c.overall_hits::cpu1.inst 107670 #
number of overall hits
-system.l2c.overall_hits::cpu1.data 52634 #
number of overall hits
-system.l2c.overall_hits::total 2080503 #
number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 13744 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 272909 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1606 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 887 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 289146 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2478 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 531 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3009 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 43 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 77 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 120 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 114968 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 7955 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 122923 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 13744 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 387877 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1606 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 8842 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 412069 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 13744 #
number of overall misses
-system.l2c.overall_misses::cpu0.data 387877 #
number of overall misses
-system.l2c.overall_misses::cpu1.inst 1606 #
number of overall misses
-system.l2c.overall_misses::cpu1.data 8842 #
number of overall misses
-system.l2c.overall_misses::total 412069 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 731783998
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 14210594000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 85626000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 48439997
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 15076443995 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 3736500 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 678500
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 441967499
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6632287996 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 731783998 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 20400914497 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 85626000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 490407496 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21708731991 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 731783998
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 20400914497
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 85626000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 490407496
# number of overall miss cycles
-system.l2c.overall_miss_latency::total 21708731991 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 984657 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1053657 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 109276 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 39954 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2187544 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 832636 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 832636 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2662 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 585 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3247 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 70
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 106
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 176 #
number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 283506 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 21522 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 305028 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 984657 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1337163 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 109276 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 61476 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2492572 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 984657 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1337163 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 109276 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 61476 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2492572 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.259011 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.022201 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.132178 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692
# miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.926702 #
miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415
# miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.681818 #
miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 #
miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.402989 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.013958 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.290075 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.014697 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.143828 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.165319 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.013958 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.290075 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.014697 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.143828 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.165319 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52141.285008
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.228410
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584
# average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1241.774676
# average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532
# average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 5654.166667
# average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677
# average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53954.817211
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52596.350124
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 55463.412803
# average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52682.274063 #
average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52596.350124
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 55463.412803
# average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52682.274063
# average overall miss latency
+system.l2c.SCUpgradeReq_hits::total 75 #
number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 135544 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 39704 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 175248 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 798441 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 832478 #
number of demand (read+write) hits
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