changeset 8fb03b13de02 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8fb03b13de02
description:
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
diffstat:
src/arch/arm/table_walker.cc | 4 +-
src/arch/arm/table_walker.hh | 4 +-
src/arch/arm/tlb.cc | 2 +-
src/arch/arm/tlb.hh | 2 +-
src/arch/x86/interrupts.hh | 6 +-
src/arch/x86/pagetable_walker.cc | 4 +-
src/arch/x86/pagetable_walker.hh | 3 +-
src/arch/x86/tlb.cc | 2 +-
src/arch/x86/tlb.hh | 2 +-
src/cpu/base.cc | 34 +++--
src/cpu/base.hh | 3 +-
src/cpu/testers/directedtest/RubyDirectedTester.cc | 4 +-
src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 +-
src/cpu/testers/memtest/memtest.cc | 4 +-
src/cpu/testers/memtest/memtest.hh | 4 +-
src/cpu/testers/networktest/networktest.cc | 4 +-
src/cpu/testers/networktest/networktest.hh | 4 +-
src/cpu/testers/rubytest/RubyTester.cc | 6 +-
src/cpu/testers/rubytest/RubyTester.hh | 4 +-
src/cpu/testers/traffic_gen/traffic_gen.cc | 4 +-
src/cpu/testers/traffic_gen/traffic_gen.hh | 4 +-
src/dev/copy_engine.cc | 6 +-
src/dev/copy_engine.hh | 6 +-
src/dev/dma_device.cc | 4 +-
src/dev/dma_device.hh | 4 +-
src/dev/io_device.cc | 4 +-
src/dev/io_device.hh | 3 +-
src/dev/pcidev.hh | 3 +-
src/dev/x86/i82094aa.hh | 3 +-
src/mem/addr_mapper.cc | 12 +-
src/mem/addr_mapper.hh | 8 +-
src/mem/bridge.cc | 8 +-
src/mem/bridge.hh | 7 +-
src/mem/bus.cc | 8 +-
src/mem/bus.hh | 6 +-
src/mem/cache/base.cc | 8 +-
src/mem/cache/base.hh | 6 +-
src/mem/comm_monitor.cc | 8 +-
src/mem/comm_monitor.hh | 8 +-
src/mem/mem_object.cc | 8 +-
src/mem/mem_object.hh | 16 +-
src/mem/port.cc | 118 +++++++++++++-------
src/mem/port.hh | 72 ++++++++++--
src/mem/ruby/system/RubyPort.cc | 12 +-
src/mem/ruby/system/RubyPort.hh | 6 +-
src/mem/simple_dram.cc | 4 +-
src/mem/simple_dram.hh | 4 +-
src/mem/simple_mem.cc | 4 +-
src/mem/simple_mem.hh | 3 +-
src/python/swig/pyobject.cc | 4 +-
src/sim/system.cc | 4 +-
src/sim/system.hh | 3 +-
src/sim/tlb.hh | 4 +-
53 files changed, 290 insertions(+), 192 deletions(-)
diffs (truncated from 1273 to 300 lines):
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/arm/table_walker.cc Mon Oct 15 08:12:35 2012 -0400
@@ -110,8 +110,8 @@
}
}
-MasterPort&
-TableWalker::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort&
+TableWalker::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
return port;
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/arm/table_walker.hh Mon Oct 15 08:12:35 2012 -0400
@@ -399,8 +399,8 @@
void completeDrain();
virtual unsigned int drain(Event *de);
virtual void resume();
- virtual MasterPort& getMasterPort(const std::string &if_name,
- int idx = -1);
+ virtual BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
TLB::Translation *_trans, bool timing, bool functional = false);
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/arm/tlb.cc Mon Oct 15 08:12:35 2012 -0400
@@ -722,7 +722,7 @@
return fault;
}
-MasterPort*
+BaseMasterPort*
TLB::getMasterPort()
{
return &tableWalker->getMasterPort("port");
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/arm/tlb.hh Mon Oct 15 08:12:35 2012 -0400
@@ -224,7 +224,7 @@
*
* @return A pointer to the walker master port
*/
- virtual MasterPort* getMasterPort();
+ virtual BaseMasterPort* getMasterPort();
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/x86/interrupts.hh Mon Oct 15 08:12:35 2012 -0400
@@ -238,7 +238,8 @@
AddrRangeList getAddrRanges() const;
AddrRangeList getIntAddrRange() const;
- MasterPort &getMasterPort(const std::string &if_name, int idx = -1)
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID)
{
if (if_name == "int_master") {
return intMasterPort;
@@ -246,7 +247,8 @@
return BasicPioDevice::getMasterPort(if_name, idx);
}
- SlavePort &getSlavePort(const std::string &if_name, int idx = -1)
+ BaseSlavePort &getSlavePort(const std::string &if_name,
+ PortID idx = InvalidPortID)
{
if (if_name == "int_slave") {
return intSlavePort;
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/x86/pagetable_walker.cc Mon Oct 15 08:12:35 2012 -0400
@@ -173,8 +173,8 @@
return port.sendTimingReq(pkt);
}
-MasterPort &
-Walker::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort &
+Walker::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "port")
return port;
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/x86/pagetable_walker.hh Mon Oct 15 08:12:35 2012 -0400
@@ -169,7 +169,8 @@
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
unsigned &logBytes, BaseTLB::Mode mode);
- MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
protected:
// The TLB we're supposed to load.
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/x86/tlb.cc Mon Oct 15 08:12:35 2012 -0400
@@ -435,7 +435,7 @@
{
}
-MasterPort *
+BaseMasterPort *
TLB::getMasterPort()
{
return &walker->getMasterPort("port");
diff -r df7c3f99ebca -r 8fb03b13de02 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/arch/x86/tlb.hh Mon Oct 15 08:12:35 2012 -0400
@@ -147,7 +147,7 @@
*
* @return A pointer to the walker master port
*/
- virtual MasterPort *getMasterPort();
+ virtual BaseMasterPort *getMasterPort();
};
}
diff -r df7c3f99ebca -r 8fb03b13de02 src/cpu/base.cc
--- a/src/cpu/base.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/cpu/base.cc Mon Oct 15 08:12:35 2012 -0400
@@ -296,8 +296,8 @@
threadContexts[0]->regStats(name());
}
-MasterPort &
-BaseCPU::getMasterPort(const string &if_name, int idx)
+BaseMasterPort &
+BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
@@ -380,17 +380,17 @@
ThreadContext::compare(oldTC, newTC);
*/
- MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
- MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
- MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
- MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
+ BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
+ BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
assert(!new_itb_port->isConnected());
assert(old_itb_port);
assert(old_itb_port->isConnected());
- SlavePort &slavePort = old_itb_port->getSlavePort();
+ BaseSlavePort &slavePort = old_itb_port->getSlavePort();
old_itb_port->unbind();
new_itb_port->bind(slavePort);
}
@@ -398,7 +398,7 @@
assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
assert(old_dtb_port->isConnected());
- SlavePort &slavePort = old_dtb_port->getSlavePort();
+ BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
old_dtb_port->unbind();
new_dtb_port->bind(slavePort);
}
@@ -408,13 +408,13 @@
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
- MasterPort *old_checker_itb_port =
+ BaseMasterPort *old_checker_itb_port =
oldChecker->getITBPtr()->getMasterPort();
- MasterPort *old_checker_dtb_port =
+ BaseMasterPort *old_checker_dtb_port =
oldChecker->getDTBPtr()->getMasterPort();
- MasterPort *new_checker_itb_port =
+ BaseMasterPort *new_checker_itb_port =
newChecker->getITBPtr()->getMasterPort();
- MasterPort *new_checker_dtb_port =
+ BaseMasterPort *new_checker_dtb_port =
newChecker->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist for checker
@@ -422,7 +422,8 @@
assert(!new_checker_itb_port->isConnected());
assert(old_checker_itb_port);
assert(old_checker_itb_port->isConnected());
- SlavePort &slavePort = old_checker_itb_port->getSlavePort();
+ BaseSlavePort &slavePort =
+ old_checker_itb_port->getSlavePort();
old_checker_itb_port->unbind();
new_checker_itb_port->bind(slavePort);
}
@@ -430,7 +431,8 @@
assert(!new_checker_dtb_port->isConnected());
assert(old_checker_dtb_port);
assert(old_checker_dtb_port->isConnected());
- SlavePort &slavePort = old_checker_dtb_port->getSlavePort();
+ BaseSlavePort &slavePort =
+ old_checker_dtb_port->getSlavePort();
old_checker_dtb_port->unbind();
new_checker_dtb_port->bind(slavePort);
}
@@ -455,13 +457,13 @@
// we are switching to.
assert(!getInstPort().isConnected());
assert(oldCPU->getInstPort().isConnected());
- SlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
oldCPU->getInstPort().unbind();
getInstPort().bind(inst_peer_port);
assert(!getDataPort().isConnected());
assert(oldCPU->getDataPort().isConnected());
- SlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
oldCPU->getDataPort().unbind();
getDataPort().bind(data_peer_port);
}
diff -r df7c3f99ebca -r 8fb03b13de02 src/cpu/base.hh
--- a/src/cpu/base.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/cpu/base.hh Mon Oct 15 08:12:35 2012 -0400
@@ -171,7 +171,8 @@
*
* @return a reference to the port with the given name
*/
- MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
inline void workItemBegin() { numWorkItemsStarted++; }
inline void workItemEnd() { numWorkItemsCompleted++; }
diff -r df7c3f99ebca -r 8fb03b13de02
src/cpu/testers/directedtest/RubyDirectedTester.cc
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc Mon Oct 15
08:12:32 2012 -0400
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc Mon Oct 15
08:12:35 2012 -0400
@@ -74,8 +74,8 @@
generator->setDirectedTester(this);
}
-MasterPort &
-RubyDirectedTester::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort &
+RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name != "cpuPort") {
// pass it along to our super class
diff -r df7c3f99ebca -r 8fb03b13de02
src/cpu/testers/directedtest/RubyDirectedTester.hh
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh Mon Oct 15
08:12:32 2012 -0400
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh Mon Oct 15
08:12:35 2012 -0400
@@ -68,8 +68,8 @@
RubyDirectedTester(const Params *p);
~RubyDirectedTester();
- virtual MasterPort &getMasterPort(const std::string &if_name,
- int idx = -1);
+ virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
MasterPort* getCpuPort(int idx);
diff -r df7c3f99ebca -r 8fb03b13de02 src/cpu/testers/memtest/memtest.cc
--- a/src/cpu/testers/memtest/memtest.cc Mon Oct 15 08:12:32 2012 -0400
+++ b/src/cpu/testers/memtest/memtest.cc Mon Oct 15 08:12:35 2012 -0400
@@ -131,8 +131,8 @@
dmaOutstanding = false;
}
-MasterPort &
-MemTest::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort &
+MemTest::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "functional")
return funcPort;
diff -r df7c3f99ebca -r 8fb03b13de02 src/cpu/testers/memtest/memtest.hh
--- a/src/cpu/testers/memtest/memtest.hh Mon Oct 15 08:12:32 2012 -0400
+++ b/src/cpu/testers/memtest/memtest.hh Mon Oct 15 08:12:35 2012 -0400
@@ -59,8 +59,8 @@
// main simulation loop (one cycle)
void tick();
- virtual MasterPort &getMasterPort(const std::string &if_name,
- int idx = -1);
+ virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
/**
* Print state of address in memory system via PrintReq (for
diff -r df7c3f99ebca -r 8fb03b13de02 src/cpu/testers/networktest/networktest.cc
--- a/src/cpu/testers/networktest/networktest.cc Mon Oct 15 08:12:32
2012 -0400
+++ b/src/cpu/testers/networktest/networktest.cc Mon Oct 15 08:12:35
2012 -0400
@@ -97,8 +97,8 @@
name(), id);
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