changeset 2e00867b5001 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2e00867b5001
description:
config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
diffstat:
configs/common/Caches.py | 5 ++---
tests/configs/o3-timing-mp.py | 6 +++---
tests/configs/pc-o3-timing.py | 6 +++---
tests/configs/pc-simple-atomic.py | 6 +++---
tests/configs/pc-simple-timing.py | 6 +++---
tests/configs/realview-o3-checker.py | 6 +++---
tests/configs/realview-o3-dual.py | 6 +++---
tests/configs/realview-o3.py | 6 +++---
tests/configs/realview-simple-atomic-dual.py | 6 +++---
tests/configs/realview-simple-atomic.py | 6 +++---
tests/configs/realview-simple-timing-dual.py | 6 +++---
tests/configs/realview-simple-timing.py | 6 +++---
tests/configs/tsunami-inorder.py | 6 +++---
tests/configs/tsunami-o3-dual.py | 6 +++---
tests/configs/tsunami-o3.py | 6 +++---
tests/configs/tsunami-simple-atomic-dual.py | 6 +++---
tests/configs/tsunami-simple-atomic.py | 6 +++---
tests/configs/tsunami-simple-timing-dual.py | 6 +++---
tests/configs/tsunami-simple-timing.py | 6 +++---
19 files changed, 56 insertions(+), 57 deletions(-)
diffs (truncated from 351 to 300 lines):
diff -r 63e7cfff4188 -r 2e00867b5001 configs/common/Caches.py
--- a/configs/common/Caches.py Thu Oct 25 13:15:59 2012 -0400
+++ b/configs/common/Caches.py Fri Oct 26 06:42:42 2012 -0400
@@ -46,7 +46,7 @@
# starting point, and specific parameters can be overridden in the
# specific instantiations.
-class L1(BaseCache):
+class L1Cache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
@@ -55,7 +55,7 @@
tgts_per_mshr = 20
is_top_level = True
-class L2(BaseCache):
+class L2Cache(BaseCache):
assoc = 8
block_size = 64
hit_latency = 20
@@ -84,4 +84,3 @@
size = '1kB'
tgts_per_mshr = 12
is_top_level = True
-
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/o3-timing-mp.py Fri Oct 26 06:42:42 2012 -0400
@@ -39,7 +39,7 @@
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
@@ -47,8 +47,8 @@
# add L1 caches
for cpu in cpus:
- cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/pc-o3-timing.py Fri Oct 26 06:42:42 2012 -0400
@@ -50,9 +50,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/pc-simple-atomic.py Fri Oct 26 06:42:42 2012 -0400
@@ -50,9 +50,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/pc-simple-timing.py Fri Oct 26 06:42:42 2012 -0400
@@ -50,9 +50,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/realview-o3-checker.py
--- a/tests/configs/realview-o3-checker.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/realview-o3-checker.py Fri Oct 26 06:42:42 2012 -0400
@@ -56,9 +56,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/realview-o3-dual.py Fri Oct 26 06:42:42 2012 -0400
@@ -46,14 +46,14 @@
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/realview-o3.py Fri Oct 26 06:42:42 2012 -0400
@@ -45,9 +45,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001
tests/configs/realview-simple-atomic-dual.py
--- a/tests/configs/realview-simple-atomic-dual.py Thu Oct 25 13:15:59
2012 -0400
+++ b/tests/configs/realview-simple-atomic-dual.py Fri Oct 26 06:42:42
2012 -0400
@@ -46,14 +46,14 @@
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/realview-simple-atomic.py Fri Oct 26 06:42:42 2012 -0400
@@ -45,9 +45,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001
tests/configs/realview-simple-timing-dual.py
--- a/tests/configs/realview-simple-timing-dual.py Thu Oct 25 13:15:59
2012 -0400
+++ b/tests/configs/realview-simple-timing-dual.py Fri Oct 26 06:42:42
2012 -0400
@@ -46,14 +46,14 @@
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/realview-simple-timing.py Fri Oct 26 06:42:42 2012 -0400
@@ -45,9 +45,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/tsunami-inorder.py
--- a/tests/configs/tsunami-inorder.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/tsunami-inorder.py Fri Oct 26 06:42:42 2012 -0400
@@ -48,9 +48,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/tsunami-o3-dual.py Fri Oct 26 06:42:42 2012 -0400
@@ -46,14 +46,14 @@
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py Thu Oct 25 13:15:59 2012 -0400
+++ b/tests/configs/tsunami-o3.py Fri Oct 26 06:42:42 2012 -0400
@@ -45,9 +45,9 @@
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/tsunami-simple-atomic-dual.py
--- a/tests/configs/tsunami-simple-atomic-dual.py Thu Oct 25 13:15:59
2012 -0400
+++ b/tests/configs/tsunami-simple-atomic-dual.py Fri Oct 26 06:42:42
2012 -0400
@@ -45,14 +45,14 @@
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
diff -r 63e7cfff4188 -r 2e00867b5001 tests/configs/tsunami-simple-atomic.py
--- a/tests/configs/tsunami-simple-atomic.py Thu Oct 25 13:15:59 2012 -0400
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
