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Does this change required any changes to the files in config/ directory? Would we not need to generate the python object for ISA at some point? - Nilay Vaish On Oct. 24, 2012, 3:07 p.m., Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1509/ > ----------------------------------------------------------- > > (Updated Oct. 24, 2012, 3:07 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9333:786d63e13657 > --------------------------- > arch: Make the ISA class inherit from SimObject > > The ISA class on stores the contents of ID registers on many > architectures. In order to make reset values of such registers > configurable, we make the class inherit from SimObject, which allows > us to use the normal generated parameter headers. > > > Diffs > ----- > > src/arch/alpha/AlphaISA.py PRE-CREATION > src/arch/alpha/SConscript f634a34f2f0b > src/arch/alpha/isa.hh f634a34f2f0b > src/arch/alpha/isa.cc f634a34f2f0b > src/arch/arm/ArmISA.py PRE-CREATION > src/arch/arm/SConscript f634a34f2f0b > src/arch/arm/isa.hh f634a34f2f0b > src/arch/arm/isa.cc f634a34f2f0b > src/arch/mips/MipsISA.py PRE-CREATION > src/arch/mips/SConscript f634a34f2f0b > src/arch/mips/isa.hh f634a34f2f0b > src/arch/mips/isa.cc f634a34f2f0b > src/arch/power/PowerISA.py PRE-CREATION > src/arch/power/SConscript f634a34f2f0b > src/arch/power/isa.hh f634a34f2f0b > src/arch/power/isa.cc PRE-CREATION > src/arch/sparc/SConscript f634a34f2f0b > src/arch/sparc/SparcISA.py PRE-CREATION > src/arch/sparc/isa.hh f634a34f2f0b > src/arch/sparc/isa.cc f634a34f2f0b > src/arch/x86/SConscript f634a34f2f0b > src/arch/x86/X86ISA.py PRE-CREATION > src/arch/x86/isa.hh f634a34f2f0b > src/arch/x86/isa.cc f634a34f2f0b > src/cpu/BaseCPU.py f634a34f2f0b > src/cpu/base.cc f634a34f2f0b > src/cpu/checker/cpu.cc f634a34f2f0b > src/cpu/inorder/cpu.hh f634a34f2f0b > src/cpu/inorder/cpu.cc f634a34f2f0b > src/cpu/inorder/thread_context.hh f634a34f2f0b > src/cpu/inorder/thread_context.cc f634a34f2f0b > src/cpu/o3/cpu.hh f634a34f2f0b > src/cpu/o3/cpu.cc f634a34f2f0b > src/cpu/o3/thread_context_impl.hh f634a34f2f0b > src/cpu/simple/base.cc f634a34f2f0b > src/cpu/simple_thread.hh f634a34f2f0b > src/cpu/simple_thread.cc f634a34f2f0b > > Diff: http://reviews.gem5.org/r/1509/diff/ > > > Testing > ------- > > > Thanks, > > Ali Saidi > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
