Hello everyone, I am looking information about cache memory design/implementation and its interconnection system with the processor(s). The more detailed the info the more useful for my needs. (Hardware design, logic circuits, signals, controller design etc are perfect!)
I imagine all the info I need depends on the system architecture... I would be happy with any kind of suggestions! Thank you in advance, Pavlos _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
