As I understand it, a typical hardware implementation tracks the lock address(es) in one or more register(s) (one per thread, so multiple in the case of SMT) in the processor itself (or somewhere around the core/cache interface). This requires a notification from the cache when a block is invalidated or evicted to clear the associated lock bit as needed.
Our implementation is intentionally different, and is optimized for software instead of hardware. Since usually a store will not invalidate a lock, we don't want to have to compare every store address against all of the lock registers. Instead, by associating the lock addresses with the cache tags, we leverage the tag lookup (which we have to do anyway) and then in the common case just do a very quick test to see that there aren't any lock addresses associated with the current block. Steve _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
