Hi all, I am a graduate student at MIT, advised by Li-Shiuan Peh. We have recently developed a power/area/delay model for NoCs and incorporate into gem5. This tool is added to replace the current NoC power/area model, Orion 2.0.
We validated Orion 2.0 and saw substantial errors compared against fabricated chip data and SPICE simulation because many technology parameters and scaling factors in Orion 2.0 are way off. We then developed a completely new NoC power/area/delay model called DSENT [NOCS'12] that uses an ASIC-based methodology for modeling. DSENT uses very few technology parameters that can be readily estimated, builds a standard cell library and sizes these cells subject to timing constraints. It has been validated against SPICE and measurements, and we currently provide 45nm, 32nm, 22nm, 11nm (Trigate), as well as photonic NoCs. The integrated DSENT takes router configurations from GARNET. The link length between two nodes are calculated in the topology scripts using a user-specified tile dimension. The frequency and technology can also be specified through python scripts. Currently only the technology parameter files still remain as text files. This work is jointly developed by our group, Prof. Vladimir Stojanovic (MIT), and Chen Sun (his student). For more detail of DSENT, please visit our website (https://sites.google.com/site/mitdsent/home). I am going to publish a review request and looking forward to your comments! Thanks, -Owen _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
