[gem5-dev] changeset in gem5: ARM: Keep a copy of the fpscr len and stride ...

[Gabe Black]

changeset 227a38f9d98c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=227a38f9d98c
description:
        ARM: Keep a copy of the fpscr len and stride fields in the decoder.
        Avoid reading them every instruction, and also eliminate the last use 
of the
        thread context in the decoders.

        Committed by: Nilay Vaish <ni...@cs.wisc.edu>

diffstat:

 src/arch/arm/decoder.cc    |   5 ++---
 src/arch/arm/decoder.hh    |  12 +++++++++++-
 src/arch/arm/isa.cc        |   1 +
 src/arch/arm/remote_gdb.cc |   2 +-
 4 files changed, 15 insertions(+), 5 deletions(-)

diffs (74 lines):

diff -r 26ba525347fe -r 227a38f9d98c src/arch/arm/decoder.cc
--- a/src/arch/arm/decoder.cc   Sun Dec 30 12:45:52 2012 -0600
+++ b/src/arch/arm/decoder.cc   Fri Jan 04 18:09:35 2013 -0600
@@ -113,9 +113,8 @@
     data = inst;
     offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
     emi.thumb = pc.thumb();
-    FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
-    emi.fpscrLen = fpscr.len;
-    emi.fpscrStride = fpscr.stride;
+    emi.fpscrLen = fpscrLen;
+    emi.fpscrStride = fpscrStride;
 
     outOfBytes = false;
     process();
diff -r 26ba525347fe -r 227a38f9d98c src/arch/arm/decoder.hh
--- a/src/arch/arm/decoder.hh   Sun Dec 30 12:45:52 2012 -0600
+++ b/src/arch/arm/decoder.hh   Fri Jan 04 18:09:35 2013 -0600
@@ -58,6 +58,9 @@
     bool foundIt;
     ITSTATE itBits;
 
+    int fpscrLen;
+    int fpscrStride;
+
   public:
     void reset()
     {
@@ -69,7 +72,8 @@
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0)
+    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
+        fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
@@ -121,6 +125,12 @@
         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
     }
 
+    void setContext(FPSCR fpscr)
+    {
+        fpscrLen = fpscr.len;
+        fpscrStride = fpscr.stride;
+    }
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;
diff -r 26ba525347fe -r 227a38f9d98c src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc       Sun Dec 30 12:45:52 2012 -0600
+++ b/src/arch/arm/isa.cc       Fri Jan 04 18:09:35 2013 -0600
@@ -381,6 +381,7 @@
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
+                tc->getDecodePtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:
diff -r 26ba525347fe -r 227a38f9d98c src/arch/arm/remote_gdb.cc
--- a/src/arch/arm/remote_gdb.cc        Sun Dec 30 12:45:52 2012 -0600
+++ b/src/arch/arm/remote_gdb.cc        Fri Jan 04 18:09:35 2013 -0600
@@ -293,7 +293,7 @@
     }
 
     //FPSCR
-    context->setMiscRegNoEffect(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
+    context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
 }
 
 void
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