changeset 6f294e7a93d1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6f294e7a93d1
description:
Decoder: Remove the thread context get/set from the decoder.
This interface is no longer used, and getting rid of it simplifies the
decoders and code that sets up the decoders. The thread context had
been used
to read architectural state which was used to contextualize the
instruction
memory as it came in. That was changed so that the state is now sent to
the
decoders to keep locally if/when it changes. That's significantly more
efficient.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/arch/alpha/decoder.hh | 18 +-----------------
src/arch/arm/decoder.cc | 1 -
src/arch/arm/decoder.hh | 17 +----------------
src/arch/arm/isa.cc | 2 +-
src/arch/mips/decoder.hh | 16 +---------------
src/arch/power/decoder.hh | 18 +-----------------
src/arch/sparc/decoder.hh | 18 +-----------------
src/arch/sparc/isa.cc | 3 ++-
src/arch/x86/decoder.cc | 1 -
src/arch/x86/decoder.hh | 16 +---------------
src/cpu/checker/cpu_impl.hh | 1 -
src/cpu/inorder/resources/fetch_unit.cc | 3 +--
src/cpu/legiontrace.cc | 1 -
src/cpu/o3/fetch_impl.hh | 5 ++---
src/cpu/simple/base.cc | 2 --
src/cpu/simple_thread.cc | 8 ++++----
16 files changed, 16 insertions(+), 114 deletions(-)
diffs (truncated from 419 to 300 lines):
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/alpha/decoder.hh
--- a/src/arch/alpha/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/alpha/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -36,36 +36,20 @@
#include "cpu/static_inst.hh"
#include "sim/full_system.hh"
-class ThreadContext;
-
namespace AlphaISA
{
class Decoder
{
protected:
- ThreadContext *tc;
-
// The extended machine instruction being generated
ExtMachInst ext_inst;
bool instDone;
public:
- Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+ Decoder() : instDone(false)
{}
- ThreadContext *
- getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
-
void
process()
{ }
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/arm/decoder.cc
--- a/src/arch/arm/decoder.cc Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/arm/decoder.cc Fri Jan 04 19:00:45 2013 -0600
@@ -32,7 +32,6 @@
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
#include "base/trace.hh"
-#include "cpu/thread_context.hh"
#include "debug/Decoder.hh"
namespace ArmISA
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/arm/decoder.hh
--- a/src/arch/arm/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/arm/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -39,15 +39,12 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
-class ThreadContext;
-
namespace ArmISA
{
class Decoder
{
protected:
- ThreadContext * tc;
//The extended machine instruction being generated
ExtMachInst emi;
MachInst data;
@@ -72,23 +69,11 @@
foundIt = false;
}
- Decoder(ThreadContext * _tc) : tc(_tc), data(0),
- fpscrLen(0), fpscrStride(0)
+ Decoder() : data(0), fpscrLen(0), fpscrStride(0)
{
reset();
}
- ThreadContext * getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
-
void process();
//Use this to give data to the decoder. This should be used
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/arm/isa.cc Fri Jan 04 19:00:45 2013 -0600
@@ -381,7 +381,7 @@
fpscrMask.n = ones;
newVal = (newVal & (uint32_t)fpscrMask) |
(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
- tc->getDecodePtr()->setContext(newVal);
+ tc->getDecoderPtr()->setContext(newVal);
}
break;
case MISCREG_CPSR_Q:
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/mips/decoder.hh
--- a/src/arch/mips/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/mips/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -37,34 +37,20 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
-class ThreadContext;
-
namespace MipsISA
{
class Decoder
{
protected:
- ThreadContext * tc;
//The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
public:
- Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+ Decoder() : instDone(false)
{}
- ThreadContext *getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext *_tc)
- {
- tc = _tc;
- }
-
void
process()
{
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/power/decoder.hh
--- a/src/arch/power/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/power/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -35,37 +35,21 @@
#include "arch/types.hh"
#include "cpu/static_inst.hh"
-class ThreadContext;
-
namespace PowerISA
{
class Decoder
{
protected:
- ThreadContext * tc;
-
// The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
public:
- Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+ Decoder() : instDone(false)
{
}
- ThreadContext *
- getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
-
void
process()
{
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/sparc/decoder.hh
--- a/src/arch/sparc/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/sparc/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -35,9 +35,6 @@
#include "arch/sparc/registers.hh"
#include "arch/types.hh"
#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-class ThreadContext;
namespace SparcISA
{
@@ -45,28 +42,15 @@
class Decoder
{
protected:
- ThreadContext * tc;
// The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
MiscReg asi;
public:
- Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
+ Decoder() : instDone(false), asi(0)
{}
- ThreadContext *
- getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
-
void process() {}
void
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/sparc/isa.cc
--- a/src/arch/sparc/isa.cc Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/sparc/isa.cc Fri Jan 04 19:00:45 2013 -0600
@@ -29,6 +29,7 @@
*/
#include "arch/sparc/asi.hh"
+#include "arch/sparc/decoder.hh"
#include "arch/sparc/isa.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
@@ -550,7 +551,7 @@
switch (miscReg) {
case MISCREG_ASI:
- tc->getDecodePtr()->setContext(val);
+ tc->getDecoderPtr()->setContext(val);
break;
case MISCREG_STICK:
case MISCREG_TICK:
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/x86/decoder.cc
--- a/src/arch/x86/decoder.cc Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/x86/decoder.cc Fri Jan 04 19:00:45 2013 -0600
@@ -33,7 +33,6 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
-#include "cpu/thread_context.hh"
#include "debug/Decoder.hh"
namespace X86ISA
diff -r 270c9a75e91f -r 6f294e7a93d1 src/arch/x86/decoder.hh
--- a/src/arch/x86/decoder.hh Fri Jan 04 19:00:44 2013 -0600
+++ b/src/arch/x86/decoder.hh Fri Jan 04 19:00:45 2013 -0600
@@ -44,8 +44,6 @@
#include "cpu/static_inst.hh"
#include "debug/Decoder.hh"
-class ThreadContext;
-
namespace X86ISA
{
@@ -72,7 +70,6 @@
static InstBytes dummy;
- ThreadContext * tc;
//The bytes to be predecoded
MachInst fetchChunk;
InstBytes *instBytes;
@@ -205,8 +202,7 @@
static InstCacheMap instCacheMap;
public:
- Decoder(ThreadContext * _tc) :
- tc(_tc), basePC(0), origPC(0), offset(0),
+ Decoder() : basePC(0), origPC(0), offset(0),
outOfBytes(true), instDone(false),
state(ResetState)
{
@@ -259,16 +255,6 @@
state = ResetState;
}
- ThreadContext * getTC()
- {
- return tc;
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