changeset 1c97b57d5169 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1c97b57d5169
description:
cpu: rename the misleading inSyscall to noSquashFromTC
isSyscall was originally created because during handling of a syscall
in SE
mode the threadcontext had to be updated. However, in many places this
is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense.
The
boolean actually stops gem5 from squashing speculative and
non-committed state
when a write to a threadcontext happens, so re-name the variable to
something
more appropriate
diffstat:
src/cpu/checker/cpu_impl.hh | 6 ++--
src/cpu/inorder/cpu.cc | 8 +++---
src/cpu/inorder/inorder_dyn_inst.cc | 12 +++++-----
src/cpu/inorder/thread_context.cc | 6 ++--
src/cpu/inorder/thread_state.hh | 14 ++++++++---
src/cpu/o3/commit_impl.hh | 18 +++++++-------
src/cpu/o3/cpu.cc | 10 ++++----
src/cpu/o3/dyn_inst.hh | 6 ++--
src/cpu/o3/dyn_inst_impl.hh | 18 +++++++-------
src/cpu/o3/thread_context.hh | 10 ++++++++
src/cpu/o3/thread_context_impl.hh | 40 ++++++++-------------------------
src/cpu/o3/thread_state.hh | 13 +++++++---
src/cpu/ozone/back_end_impl.hh | 8 +++---
src/cpu/ozone/cpu_impl.hh | 26 +++++++++++-----------
src/cpu/ozone/dyn_inst_impl.hh | 12 +++++-----
src/cpu/ozone/inorder_back_end_impl.hh | 24 ++++++++++----------
src/cpu/ozone/lw_back_end_impl.hh | 18 +++++++-------
src/cpu/ozone/thread_state.hh | 6 ++--
18 files changed, 128 insertions(+), 127 deletions(-)
diffs (truncated from 857 to 300 lines):
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/checker/cpu_impl.hh Mon Jan 07 13:05:33 2013 -0500
@@ -573,12 +573,12 @@
"registers from main CPU", curTick(), unverifiedInst->instAddr());
// Terribly convoluted way to make sure O3 model does not implode
- bool inSyscall = unverifiedInst->thread->inSyscall;
- unverifiedInst->thread->inSyscall = true;
+ bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
+ unverifiedInst->thread->noSquashFromTC = true;
// Heavy-weight copying of all registers
thread->copyArchRegs(unverifiedInst->tcBase());
- unverifiedInst->thread->inSyscall = inSyscall;
+ unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
// Set curStaticInst to unverifiedInst->staticInst
curStaticInst = unverifiedInst->staticInst;
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/inorder/cpu.cc Mon Jan 07 13:05:33 2013 -0500
@@ -786,9 +786,9 @@
BaseCPU::init();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
- // Set inSyscall so that the CPU doesn't squash when initially
+ // Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Initialise the ThreadContext's memory proxies
thread[tid]->initMemProxies(thread[tid]->getTC());
}
@@ -800,9 +800,9 @@
}
}
- // Clear inSyscall.
+ // Clear noSquashFromTC.
for (ThreadID tid = 0; tid < numThreads; ++tid)
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
// Call Initializiation Routine for Resource Pool
resPool->init();
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Mon Jan 07 13:05:33 2013 -0500
@@ -220,12 +220,12 @@
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->execute(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -244,12 +244,12 @@
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->initiateAcc(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/inorder/thread_context.cc
--- a/src/cpu/inorder/thread_context.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/inorder/thread_context.cc Mon Jan 07 13:05:33 2013 -0500
@@ -90,10 +90,10 @@
copyArchRegs(old_context);
thread->funcExeInst = old_context->readFuncExeInst();
-
+
old_context->setStatus(ThreadContext::Halted);
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
thread->trapPending = false;
}
@@ -159,7 +159,7 @@
void
InOrderThreadContext::unserialize(Checkpoint *cp, const std::string §ion)
{
- panic("unserialize unimplemented");
+ panic("unserialize unimplemented");
}
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/inorder/thread_state.hh
--- a/src/cpu/inorder/thread_state.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/inorder/thread_state.hh Mon Jan 07 13:05:33 2013 -0500
@@ -61,10 +61,15 @@
InOrderCPU *cpu;
public:
- /** Whether or not the thread is currently in syscall mode, and
- * thus able to be externally updated without squashing.
+ /* This variable controls if writes to a thread context should cause a all
+ * dynamic/speculative state to be thrown away. Nominally this is the
+ * desired behavior because the external thread context write has updated
+ * some state that could be used by an inflight instruction, however there
+ * are some cases like in a fault/trap handler where this behavior would
+ * lead to successive restarts and forward progress couldn't be made. This
+ * variable controls if the squashing will occur.
*/
- bool inSyscall;
+ bool noSquashFromTC;
/** Whether or not the thread is currently waiting on a trap, and
* thus able to be externally updated without squashing.
@@ -75,7 +80,8 @@
Process *_process)
: ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num,
_process),
- cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false)
+ cpu(_cpu), noSquashFromTC(false), trapPending(false),
+ lastGradIsBranch(false)
{ }
/** Handles the syscall. */
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/o3/commit_impl.hh Mon Jan 07 13:05:33 2013 -0500
@@ -559,7 +559,7 @@
DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
thread[tid]->trapPending = false;
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
trapInFlight[tid] = false;
trapSquash[tid] = false;
@@ -576,7 +576,7 @@
DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
assert(!thread[tid]->trapPending);
commitStatus[tid] = ROBSquashing;
@@ -721,8 +721,8 @@
// Clear the interrupt now that it's going to be handled
toIEW->commitInfo[0].clearInterrupt = true;
- assert(!thread[0]->inSyscall);
- thread[0]->inSyscall = true;
+ assert(!thread[0]->noSquashFromTC);
+ thread[0]->noSquashFromTC = true;
if (cpu->checker) {
cpu->checker->handlePendingInt();
@@ -731,7 +731,7 @@
// CPU will handle interrupt.
cpu->processInterrupts(interrupt);
- thread[0]->inSyscall = false;
+ thread[0]->noSquashFromTC = false;
commitStatus[0] = TrapPending;
@@ -1014,7 +1014,7 @@
Addr oldpc;
// Debug statement. Checks to make sure we're not
// currently updating state while handling PC events.
- assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
+ assert(!thread[tid]->noSquashFromTC &&
!thread[tid]->trapPending);
do {
oldpc = pc[tid].instAddr();
cpu->system->pcEventQueue.service(thread[tid]->getTC());
@@ -1140,11 +1140,11 @@
cpu->checker->verify(head_inst);
}
- assert(!thread[tid]->inSyscall);
+ assert(!thread[tid]->noSquashFromTC);
// Mark that we're in state update mode so that the trap's
// execution doesn't generate extra squashes.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Execute the trap. Although it's slightly unrealistic in
// terms of timing (as it doesn't wait for the full timing of
@@ -1155,7 +1155,7 @@
cpu->trap(inst_fault, tid, head_inst->staticInst);
// Exit state update mode to avoid accidental updating.
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
commitStatus[tid] = TrapPending;
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/o3/cpu.cc Mon Jan 07 13:05:33 2013 -0500
@@ -644,9 +644,9 @@
BaseCPU::init();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
- // Set inSyscall so that the CPU doesn't squash when initially
+ // Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Initialise the ThreadContext's memory proxies
thread[tid]->initMemProxies(thread[tid]->getTC());
}
@@ -665,9 +665,9 @@
}
}
- // Clear inSyscall.
+ // Clear noSquashFromTC.
for (int tid = 0; tid < numThreads; ++tid)
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
// Initialize stages.
fetch.initStage();
@@ -1464,7 +1464,7 @@
void
FullO3CPU<Impl>::squashFromTC(ThreadID tid)
{
- this->thread[tid]->inSyscall = true;
+ this->thread[tid]->noSquashFromTC = true;
this->commit.generateTCEvent(tid);
}
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/o3/dyn_inst.hh
--- a/src/cpu/o3/dyn_inst.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/o3/dyn_inst.hh Mon Jan 07 13:05:33 2013 -0500
@@ -183,14 +183,14 @@
// using the TC during an instruction's execution (specifically for
// instructions that have side-effects that use the TC). Fix this.
// See cpu/o3/dyn_inst_impl.hh.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
for (int i = 0; i < _numDestMiscRegs; i++)
this->cpu->setMiscReg(
_destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
}
void forwardOldRegs()
diff -r ffec48040ac1 -r 1c97b57d5169 src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/cpu/o3/dyn_inst_impl.hh Mon Jan 07 13:05:33 2013 -0500
@@ -130,12 +130,12 @@
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->execute(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -148,12 +148,12 @@
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->initiateAcc(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
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