changeset d631aac65246 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d631aac65246
description:
cpu: Check that the memory system is in the correct mode
This patch adds checks to all CPU models to make sure that the memory
system is in the correct mode at startup and when resuming after a
drain. Previously, we only checked that the memory system was in the
right mode when resuming. This is inadequate since this is a
configuration error that should be detected at startup as well as when
resuming. Additionally, since the check was done using an assert, it
wasn't performed when NDEBUG was set (e.g., the fast target).
diffstat:
src/cpu/inorder/cpu.cc | 6 ++++++
src/cpu/o3/cpu.cc | 11 ++++++++++-
src/cpu/simple/atomic.cc | 11 ++++++++++-
src/cpu/simple/timing.cc | 11 ++++++++++-
4 files changed, 36 insertions(+), 3 deletions(-)
diffs (100 lines):
diff -r 43caa4ca5979 -r d631aac65246 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Jan 07 13:05:40 2013 -0500
+++ b/src/cpu/inorder/cpu.cc Mon Jan 07 13:05:41 2013 -0500
@@ -787,6 +787,12 @@
{
BaseCPU::init();
+ if (!params()->defer_registration &&
+ system->getMemoryMode() != Enums::timing) {
+ fatal("The in-order CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
+
for (ThreadID tid = 0; tid < numThreads; ++tid) {
// Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
diff -r 43caa4ca5979 -r d631aac65246 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Jan 07 13:05:40 2013 -0500
+++ b/src/cpu/o3/cpu.cc Mon Jan 07 13:05:41 2013 -0500
@@ -647,6 +647,12 @@
{
BaseCPU::init();
+ if (!params()->defer_registration &&
+ system->getMemoryMode() != Enums::timing) {
+ fatal("The O3 CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
+
for (ThreadID tid = 0; tid < numThreads; ++tid) {
// Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
@@ -1174,7 +1180,10 @@
if (_status == SwitchedOut)
return;
- assert(system->getMemoryMode() == Enums::timing);
+ if (system->getMemoryMode() != Enums::timing) {
+ fatal("The O3 CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
diff -r 43caa4ca5979 -r d631aac65246 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Mon Jan 07 13:05:40 2013 -0500
+++ b/src/cpu/simple/atomic.cc Mon Jan 07 13:05:41 2013 -0500
@@ -83,6 +83,12 @@
{
BaseCPU::init();
+ if (!params()->defer_registration &&
+ system->getMemoryMode() != Enums::atomic) {
+ fatal("The atomic CPU requires the memory system to be in "
+ "'atomic' mode.\n");
+ }
+
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
@@ -155,7 +161,10 @@
return;
DPRINTF(SimpleCPU, "Resume\n");
- assert(system->getMemoryMode() == Enums::atomic);
+ if (system->getMemoryMode() != Enums::atomic) {
+ fatal("The atomic CPU requires the memory system to be in "
+ "'atomic' mode.\n");
+ }
setDrainState(Drainable::Running);
if (thread->status() == ThreadContext::Active) {
diff -r 43caa4ca5979 -r d631aac65246 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Mon Jan 07 13:05:40 2013 -0500
+++ b/src/cpu/simple/timing.cc Mon Jan 07 13:05:41 2013 -0500
@@ -66,6 +66,12 @@
{
BaseCPU::init();
+ if (!params()->defer_registration &&
+ system->getMemoryMode() != Enums::timing) {
+ fatal("The timing CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
+
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
@@ -140,7 +146,10 @@
{
DPRINTF(SimpleCPU, "Resume\n");
if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == Enums::timing);
+ if (system->getMemoryMode() != Enums::timing) {
+ fatal("The timing CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
if (fetchEvent.scheduled())
deschedule(fetchEvent);
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