changeset 644f2a2c9bfc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=644f2a2c9bfc
description:
cpu: Flush TLBs on switchOut()
This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching. Additionally, the
TLB flushing functionality is exported to the Python to make debugging
of switching/checkpointing easier.
A simulation script will typically use the TLB flushing functionality
to generate a reference trace. The following sequence can be used to
simulate a handover (this depends on how drain is implemented, but is
generally the case) between identically configured CPU models:
m5.drain(test_sys)
[ cpu.flushTLBs() for cpu in test_sys.cpu ]
m5.resume(test_sys)
The generated trace should normally be identical to a trace generated
when switching between identically configured CPU models or
checkpointing and resuming.
diffstat:
src/arch/sparc/tlb.hh | 7 ++++---
src/cpu/BaseCPU.py | 1 +
src/cpu/base.cc | 20 ++++++++++++++++++++
src/cpu/base.hh | 11 +++++++++++
4 files changed, 36 insertions(+), 3 deletions(-)
diffs (93 lines):
diff -r 5963165c00cb -r 644f2a2c9bfc src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Mon Jan 07 13:05:47 2013 -0500
+++ b/src/arch/sparc/tlb.hh Mon Jan 07 13:05:48 2013 -0500
@@ -114,6 +114,10 @@
*/
TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
bool update_used = true);
+
+ /** Remove all entries from the TLB */
+ void flushAll();
+
protected:
/** Insert a PTE into the TLB. */
void insert(Addr vpn, int partition_id, int context_id, bool real,
@@ -122,9 +126,6 @@
/** Given an entry id, read that tlb entries' tag. */
uint64_t TagRead(int entry);
- /** Remove all entries from the TLB */
- void flushAll();
-
/** Remove all non-locked entries from the tlb that match partition id. */
void demapAll(int partition_id);
diff -r 5963165c00cb -r 644f2a2c9bfc src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Mon Jan 07 13:05:47 2013 -0500
+++ b/src/cpu/BaseCPU.py Mon Jan 07 13:05:48 2013 -0500
@@ -96,6 +96,7 @@
void switchOut();
void takeOverFrom(BaseCPU *cpu);
bool switchedOut();
+ void flushTLBs();
''')
def takeOverFrom(self, old_cpu):
diff -r 5963165c00cb -r 644f2a2c9bfc src/cpu/base.cc
--- a/src/cpu/base.cc Mon Jan 07 13:05:47 2013 -0500
+++ b/src/cpu/base.cc Mon Jan 07 13:05:48 2013 -0500
@@ -361,6 +361,10 @@
_switchedOut = true;
if (profileEvent && profileEvent->scheduled())
deschedule(profileEvent);
+
+ // Flush all TLBs in the CPU to avoid having stale translations if
+ // it gets switched in later.
+ flushTLBs();
}
void
@@ -482,6 +486,22 @@
getDataPort().bind(data_peer_port);
}
+void
+BaseCPU::flushTLBs()
+{
+ for (ThreadID i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext &tc(*threadContexts[i]);
+ CheckerCPU *checker(tc.getCheckerCpuPtr());
+
+ tc.getITBPtr()->flushAll();
+ tc.getDTBPtr()->flushAll();
+ if (checker) {
+ checker->getITBPtr()->flushAll();
+ checker->getDTBPtr()->flushAll();
+ }
+ }
+}
+
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
: cpu(_cpu), interval(_interval)
diff -r 5963165c00cb -r 644f2a2c9bfc src/cpu/base.hh
--- a/src/cpu/base.hh Mon Jan 07 13:05:47 2013 -0500
+++ b/src/cpu/base.hh Mon Jan 07 13:05:48 2013 -0500
@@ -324,6 +324,17 @@
virtual void takeOverFrom(BaseCPU *cpu);
/**
+ * Flush all TLBs in the CPU.
+ *
+ * This method is mainly used to flush stale translations when
+ * switching CPUs. It is also exported to the Python world to
+ * allow it to request a TLB flush after draining the CPU to make
+ * it easier to compare traces when debugging
+ * handover/checkpointing.
+ */
+ void flushTLBs();
+
+ /**
* Determine if the CPU is switched out.
*
* @return True if the CPU is switched out, false otherwise.
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