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Any opinions? - Nilay Vaish On Dec. 3, 2012, 1:51 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1544/ > ----------------------------------------------------------- > > (Updated Dec. 3, 2012, 1:51 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9360:9dc3879af7c9 > --------------------------- > ruby: move files from ruby/system to ruby/structures > I felt that the directory ruby/system is getting crowded. Hence, I am thinking > of the moving some of the files to ruby/structures directory. This includes > Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, > Perfect Cache Memory, Timer Table, Bank Array. > > > Diffs > ----- > > src/mem/ruby/SConscript 94383c5124d2 > src/mem/ruby/common/NetDest.hh 94383c5124d2 > src/mem/ruby/profiler/Profiler.hh 94383c5124d2 > src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh 94383c5124d2 > src/mem/ruby/structures/AbstractReplacementPolicy.hh PRE-CREATION > src/mem/ruby/structures/BankedArray.hh PRE-CREATION > src/mem/ruby/structures/BankedArray.cc PRE-CREATION > src/mem/ruby/structures/Cache.py PRE-CREATION > src/mem/ruby/structures/CacheMemory.hh PRE-CREATION > src/mem/ruby/structures/CacheMemory.cc PRE-CREATION > src/mem/ruby/structures/DirectoryMemory.hh PRE-CREATION > src/mem/ruby/structures/DirectoryMemory.cc PRE-CREATION > src/mem/ruby/structures/DirectoryMemory.py PRE-CREATION > src/mem/ruby/structures/LRUPolicy.hh PRE-CREATION > src/mem/ruby/structures/MachineID.hh PRE-CREATION > src/mem/ruby/structures/MemoryControl.hh PRE-CREATION > src/mem/ruby/structures/MemoryControl.cc PRE-CREATION > src/mem/ruby/structures/MemoryControl.py PRE-CREATION > src/mem/ruby/structures/MemoryNode.hh PRE-CREATION > src/mem/ruby/structures/MemoryNode.cc PRE-CREATION > src/mem/ruby/structures/MemoryVector.hh PRE-CREATION > src/mem/ruby/structures/PerfectCacheMemory.hh PRE-CREATION > src/mem/ruby/structures/PersistentTable.hh PRE-CREATION > src/mem/ruby/structures/PersistentTable.cc PRE-CREATION > src/mem/ruby/structures/PseudoLRUPolicy.hh PRE-CREATION > src/mem/ruby/structures/RubyMemoryControl.hh PRE-CREATION > src/mem/ruby/structures/RubyMemoryControl.cc PRE-CREATION > src/mem/ruby/structures/RubyMemoryControl.py PRE-CREATION > src/mem/ruby/structures/SConscript PRE-CREATION > src/mem/ruby/structures/SparseMemory.hh PRE-CREATION > src/mem/ruby/structures/SparseMemory.cc PRE-CREATION > src/mem/ruby/structures/TBETable.hh PRE-CREATION > src/mem/ruby/structures/TimerTable.hh PRE-CREATION > src/mem/ruby/structures/TimerTable.cc PRE-CREATION > src/mem/ruby/structures/WireBuffer.hh PRE-CREATION > src/mem/ruby/structures/WireBuffer.cc PRE-CREATION > src/mem/ruby/structures/WireBuffer.py PRE-CREATION > src/mem/ruby/system/AbstractReplacementPolicy.hh 94383c5124d2 > src/mem/ruby/system/BankedArray.hh 94383c5124d2 > src/mem/ruby/system/BankedArray.cc 94383c5124d2 > src/mem/ruby/system/Cache.py 94383c5124d2 > src/mem/ruby/system/CacheMemory.hh 94383c5124d2 > src/mem/ruby/system/CacheMemory.cc 94383c5124d2 > src/mem/ruby/system/DirectoryMemory.hh 94383c5124d2 > src/mem/ruby/system/DirectoryMemory.cc 94383c5124d2 > src/mem/ruby/system/DirectoryMemory.py 94383c5124d2 > src/mem/ruby/system/LRUPolicy.hh 94383c5124d2 > src/mem/ruby/system/MachineID.hh 94383c5124d2 > src/mem/ruby/system/MemoryControl.hh 94383c5124d2 > src/mem/ruby/system/MemoryControl.cc 94383c5124d2 > src/mem/ruby/system/MemoryControl.py 94383c5124d2 > src/mem/ruby/system/MemoryNode.hh 94383c5124d2 > src/mem/ruby/system/MemoryNode.cc 94383c5124d2 > src/mem/ruby/system/MemoryVector.hh 94383c5124d2 > src/mem/ruby/system/PerfectCacheMemory.hh 94383c5124d2 > src/mem/ruby/system/PersistentTable.hh 94383c5124d2 > src/mem/ruby/system/PersistentTable.cc 94383c5124d2 > src/mem/ruby/system/PseudoLRUPolicy.hh 94383c5124d2 > src/mem/ruby/system/RubyMemoryControl.hh 94383c5124d2 > src/mem/ruby/system/RubyMemoryControl.cc 94383c5124d2 > src/mem/ruby/system/RubyMemoryControl.py 94383c5124d2 > src/mem/ruby/system/SConscript 94383c5124d2 > src/mem/ruby/system/Sequencer.hh 94383c5124d2 > src/mem/ruby/system/SparseMemory.hh 94383c5124d2 > src/mem/ruby/system/SparseMemory.cc 94383c5124d2 > src/mem/ruby/system/System.hh 94383c5124d2 > src/mem/ruby/system/TBETable.hh 94383c5124d2 > src/mem/ruby/system/TimerTable.hh 94383c5124d2 > src/mem/ruby/system/TimerTable.cc 94383c5124d2 > src/mem/ruby/system/WireBuffer.hh 94383c5124d2 > src/mem/ruby/system/WireBuffer.cc 94383c5124d2 > src/mem/ruby/system/WireBuffer.py 94383c5124d2 > src/mem/slicc/symbols/Type.py 94383c5124d2 > > Diff: http://reviews.gem5.org/r/1544/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
