[gem5-dev] changeset in gem5: x86: implements emms instruction

[Nilay Vaish]

changeset 4193ed60eed7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4193ed60eed7
description:
        x86: implements emms instruction

diffstat:

 src/arch/x86/isa/decoder/two_byte_opcodes.isa             |  2 +-
 src/arch/x86/isa/insts/simd64/integer/exit_media_state.py |  5 ++++-
 src/arch/x86/isa/microasm.isa                             |  1 +
 src/arch/x86/isa/microops/mediaop.isa                     |  6 ++++++
 src/arch/x86/isa/operands.isa                             |  1 +
 5 files changed, 13 insertions(+), 2 deletions(-)

diffs (62 lines):

diff -r 68f7e0bcf4aa -r 4193ed60eed7 
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa     Tue Jan 15 07:43:19 
2013 -0600
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa     Tue Jan 15 07:43:20 
2013 -0600
@@ -604,7 +604,7 @@
                         0x4: Inst::PCMPEQB(Pq,Qq);
                         0x5: Inst::PCMPEQW(Pq,Qq);
                         0x6: Inst::PCMPEQD(Pq,Qq);
-                        0x7: WarnUnimpl::emms();
+                        0x7: Inst::EMMS();
                     }
                     // repe (0xF3)
                     0x4: decode OPCODE_OP_BOTTOM3 {
diff -r 68f7e0bcf4aa -r 4193ed60eed7 
src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
--- a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py Tue Jan 15 
07:43:19 2013 -0600
+++ b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py Tue Jan 15 
07:43:20 2013 -0600
@@ -36,6 +36,9 @@
 # Authors: Gabe Black
 
 microcode = '''
-# EMMS
+def macroop EMMS {
+    emms
+};
+
 # FEMMS
 '''
diff -r 68f7e0bcf4aa -r 4193ed60eed7 src/arch/x86/isa/microasm.isa
--- a/src/arch/x86/isa/microasm.isa     Tue Jan 15 07:43:19 2013 -0600
+++ b/src/arch/x86/isa/microasm.isa     Tue Jan 15 07:43:20 2013 -0600
@@ -212,6 +212,7 @@
 
     assembler.symbols["fsw"] = readFpReg("FSW")
     assembler.symbols["fcw"] = readFpReg("FCW")
+    assembler.symbols["ftw"] = readFpReg("FTW")
 
     macroopDict = assembler.assemble(microcode)
 
diff -r 68f7e0bcf4aa -r 4193ed60eed7 src/arch/x86/isa/microops/mediaop.isa
--- a/src/arch/x86/isa/microops/mediaop.isa     Tue Jan 15 07:43:19 2013 -0600
+++ b/src/arch/x86/isa/microops/mediaop.isa     Tue Jan 15 07:43:20 2013 -0600
@@ -1502,4 +1502,10 @@
             else if(arg1 == arg2)
                 ccFlagBits = ccFlagBits | ZFBit;
         '''
+
+    class Emms(MediaOp):
+        def __init__(self):
+            super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
+                    'InstRegIndex(0)', 'InstRegIndex(0)', 0)
+        code = 'FTW = 0xFFFF;'
 }};
diff -r 68f7e0bcf4aa -r 4193ed60eed7 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa     Tue Jan 15 07:43:19 2013 -0600
+++ b/src/arch/x86/isa/operands.isa     Tue Jan 15 07:43:20 2013 -0600
@@ -162,6 +162,7 @@
         # Registers related to the state of x87 floating point unit.
         'TOP':           controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
         'FSW':           controlReg('MISCREG_FSW', 67, ctype='uw'),
+        'FTW':           controlReg('MISCREG_FTW', 68, ctype='uw'),
 
         # The segment base as used by memory instructions.
         'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
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