Thanks for getting this done Nilay.
Ali On 24.01.2013 12:25, Nilay Vaish wrote: > changeset d059f8a95a42 in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=d059f8a95a42 [1] > description: > branch predictor: move out of o3 and inorder cpus > This patch moves the branch predictor files in the o3 and inorder directories > to src/cpu/pred. This allows sharing the branch predictor across different > cpu models. > > This patch was originally posted by Timothy Jones in July 2010 > but never made it to the repository. > > diffstat: > > configs/common/O3_ARM_v7a.py | 7 +- > src/cpu/BaseCPU.py | 3 + > src/cpu/inorder/InOrderCPU.py | 21 +- > src/cpu/inorder/SConscript | 1 - > src/cpu/inorder/inorder_cpu_builder.cc | 6 - > src/cpu/inorder/resources/bpred_unit.cc | 463 ---------------------- > src/cpu/inorder/resources/bpred_unit.hh | 267 ------------ > src/cpu/inorder/resources/branch_predictor.cc | 25 +- > src/cpu/inorder/resources/branch_predictor.hh | 4 +- > src/cpu/o3/O3CPU.py | 20 +- > src/cpu/o3/SConscript | 1 - > src/cpu/o3/bpred_unit.cc | 34 - > src/cpu/o3/bpred_unit.hh | 299 -------------- > src/cpu/o3/bpred_unit_impl.hh | 515 ------------------------ > src/cpu/o3/cpu_policy.hh | 5 - > src/cpu/o3/deriv.cc | 2 - > src/cpu/o3/fetch.hh | 4 +- > src/cpu/o3/fetch_impl.hh | 21 +- > src/cpu/o3/sat_counter.cc | 57 -- > src/cpu/o3/sat_counter.hh | 117 ----- > src/cpu/pred/2bit_local.cc | 47 +- > src/cpu/pred/2bit_local.hh | 26 +- > src/cpu/pred/BranchPredictor.py | 54 ++ > src/cpu/pred/SConscript | 4 + > src/cpu/pred/bpred_unit.cc | 49 ++ > src/cpu/pred/bpred_unit.hh | 286 +++++++++++++ > src/cpu/pred/bpred_unit_impl.hh | 536 ++++++++++++++++++++++++++ > src/cpu/pred/btb.hh | 6 +- > src/cpu/pred/ras.hh | 6 +- > src/cpu/pred/sat_counter.hh | 117 +++++ > src/cpu/pred/tournament.cc | 37 +- > src/cpu/pred/tournament.hh | 31 +- > 32 files changed, 1157 insertions(+), 1914 deletions(-) > > diffs (truncated from 3710 to 300 lines): > > diff -r f9e76b1eb79a -r d059f8a95a42 configs/common/O3_ARM_v7a.py > --- a/configs/common/O3_ARM_v7a.py Tue Jan 22 00:13:28 2013 -0600 > +++ b/configs/common/O3_ARM_v7a.py Thu Jan 24 12:28:51 2013 -0600 > @@ -87,8 +87,8 @@ > FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(), > O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()] > > - > -class O3_ARM_v7a_3(DerivO3CPU): > +# Tournament Branch Predictor > +class O3_ARM_v7a_BP(BranchPredictor): > predType = "tournament" > localCtrBits = 2 > localHistoryTableSize = 64 > @@ -102,6 +102,8 @@ > BTBTagSize = 18 > RASSize = 16 > instShiftAmt = 2 > + > +class O3_ARM_v7a_3(DerivO3CPU): > LQEntries = 16 > SQEntries = 16 > LSQDepCheckShift = 0 > @@ -142,6 +144,7 @@ > numROBEntries = 40 > > switched_out = False > + branchPred = O3_ARM_v7a_BP() > > # Instruction Cache > class O3_ARM_v7a_ICache(BaseCache): > diff -r f9e76b1eb79a -r d059f8a95a42 src/cpu/BaseCPU.py > --- a/src/cpu/BaseCPU.py Tue Jan 22 00:13:28 2013 -0600 > +++ b/src/cpu/BaseCPU.py Thu Jan 24 12:28:51 2013 -0600 > @@ -51,6 +51,7 @@ > from InstTracer import InstTracer > from ExeTracer import ExeTracer > from MemObject import MemObject > +from BranchPredictor import BranchPredictor > > default_tracer = ExeTracer() > > @@ -184,6 +185,8 @@ > dcache_port = MasterPort("Data Port") > _cached_ports = ['icache_port', 'dcache_port'] > > + branchPred = Param.BranchPredictor(NULL, "Branch Predictor") > + > if buildEnv['TARGET_ISA'] in ['x86', 'arm']: > _cached_ports += ["itb.walker.port", "dtb.walker.port"] > > diff -r f9e76b1eb79a -r d059f8a95a42 src/cpu/inorder/InOrderCPU.py > --- a/src/cpu/inorder/InOrderCPU.py Tue Jan 22 00:13:28 2013 -0600 > +++ b/src/cpu/inorder/InOrderCPU.py Thu Jan 24 12:28:51 2013 -0600 > @@ -29,6 +29,7 @@ > from m5.params import * > from m5.proxy import * > from BaseCPU import BaseCPU > +from BranchPredictor import BranchPredictor > > class ThreadModel(Enum): > vals = ['Single', 'SMT', 'SwitchOnCacheMiss'] > @@ -46,24 +47,6 @@ > fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)") > memBlockSize = Param.Unsigned(64, "Memory Block Size") > > - predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") > - localPredictorSize = Param.Unsigned(2048, "Size of local predictor") > - localCtrBits = Param.Unsigned(2, "Bits per counter") > - localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") > - localHistoryBits = Param.Unsigned(11, "Bits for the local history") > - globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") > - globalCtrBits = Param.Unsigned(2, "Bits per counter") > - globalHistoryBits = Param.Unsigned(13, "Bits of history") > - choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") > - choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") > - > - BTBEntries = Param.Unsigned(4096, "Number of BTB entries") > - BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") > - > - RASSize = Param.Unsigned(16, "RAS size") > - > - instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") > - > stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU") > > multLatency = Param.Cycles(1, "Latency for Multiply Operations") > @@ -76,3 +59,5 @@ > div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations") > div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") > div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") > + > + branchPred = BranchPredictor(numThreads = Parent.numThreads) > diff -r f9e76b1eb79a -r d059f8a95a42 src/cpu/inorder/SConscript > --- a/src/cpu/inorder/SConscript Tue Jan 22 00:13:28 2013 -0600 > +++ b/src/cpu/inorder/SConscript Thu Jan 24 12:28:51 2013 -0600 > @@ -71,7 +71,6 @@ > Source('resource.cc') > Source('resources/agen_unit.cc') > Source('resources/execution_unit.cc') > - Source('resources/bpred_unit.cc') > Source('resources/branch_predictor.cc') > Source('resources/cache_unit.cc') > Source('resources/fetch_unit.cc') > diff -r f9e76b1eb79a -r d059f8a95a42 src/cpu/inorder/inorder_cpu_builder.cc > --- a/src/cpu/inorder/inorder_cpu_builder.cc Tue Jan 22 00:13:28 2013 -0600 > +++ b/src/cpu/inorder/inorder_cpu_builder.cc Thu Jan 24 12:28:51 2013 -0600 > @@ -57,11 +57,5 @@ > } > > numThreads = actual_num_threads; > - > - instShiftAmt = 2; > - > return new InOrderCPU(this); > } > - > - > - > diff -r f9e76b1eb79a -r d059f8a95a42 src/cpu/inorder/resources/bpred_unit.cc > --- a/src/cpu/inorder/resources/bpred_unit.cc Tue Jan 22 00:13:28 2013 -0600 > +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 > @@ -1,463 +0,0 @@ > - > -/* > - * Copyright (c) 2004-2005 The Regents of The University of Michigan > - * All rights reserved. > - * > - * Redistribution and use in source and binary forms, with or without > - * modification, are permitted provided that the following conditions are > - * met: redistributions of source code must retain the above copyright > - * notice, this list of conditions and the following disclaimer; > - * redistributions in binary form must reproduce the above copyright > - * notice, this list of conditions and the following disclaimer in the > - * documentation and/or other materials provided with the distribution; > - * neither the name of the copyright holders nor the names of its > - * contributors may be used to endorse or promote products derived from > - * this software without specific prior written permission. > - * > - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > - * > - * Authors: Kevin Lim > - */ > - > -#include <list> > -#include <vector> > - > -#include "arch/utility.hh" > -#include "base/trace.hh" > -#include "config/the_isa.hh" > -#include "cpu/inorder/resources/bpred_unit.hh" > -#include "debug/InOrderBPred.hh" > -#include "debug/Resource.hh" > - > -using namespace std; > -using namespace ThePipeline; > - > -BPredUnit::BPredUnit(Resource *_res, ThePipeline::Params *params) > - : res(_res), > - BTB(params->BTBEntries, params->BTBTagSize, params->instShiftAmt) > -{ > - // Setup the selected predictor. > - if (params->predType == "local") { > - localBP = new LocalBP(params->localPredictorSize, > - params->localCtrBits, > - params->instShiftAmt); > - predictor = Local; > - } else if (params->predType == "tournament") { > - tournamentBP = new TournamentBP(params->localCtrBits, > - params->localHistoryTableSize, > - params->localHistoryBits, > - params->globalPredictorSize, > - params->globalHistoryBits, > - params->globalCtrBits, > - params->choicePredictorSize, > - params->choiceCtrBits, > - params->instShiftAmt); > - predictor = Tournament; > - } else { > - fatal("Invalid BP selected!"); > - } > - > - for (int i=0; i < ThePipeline::MaxThreads; i++) > - RAS[i].init(params->RASSize); > - > - instSize = sizeof(TheISA::MachInst); > -} > - > -std::string > -BPredUnit::name() > -{ > - return res->name(); > -} > - > -void > -BPredUnit::regStats() > -{ > - lookups > - .name(name() + ".lookups") > - .desc("Number of BP lookups") > - ; > - > - condPredicted > - .name(name() + ".condPredicted") > - .desc("Number of conditional branches predicted") > - ; > - > - condIncorrect > - .name(name() + ".condIncorrect") > - .desc("Number of conditional branches incorrect") > - ; > - > - BTBLookups > - .name(name() + ".BTBLookups") > - .desc("Number of BTB lookups") > - ; > - > - BTBHits > - .name(name() + ".BTBHits") > - .desc("Number of BTB hits") > - ; > - > - BTBHitPct > - .name(name() + ".BTBHitPct") > - .desc("BTB Hit Percentage") > - .precision(6); > - BTBHitPct = (BTBHits / BTBLookups) * 100; > - > - usedRAS > - .name(name() + ".usedRAS") > - .desc("Number of times the RAS was used to get a target.") > - ; > - > - RASIncorrect > - .name(name() + ".RASInCorrect") > - .desc("Number of incorrect RAS predictions.") > - ; > -} > - > - > -void > -BPredUnit::switchOut() > -{ > - // Clear any state upon switch out. > - for (int i = 0; i < ThePipeline::MaxThreads; ++i) { > - squash(0, i); > - } > -} > - > - > -void > -BPredUnit::takeOverFrom() > -{ > - // Can reset all predictor state, but it's not necessarily better > - // than leaving it be. > -/* > - for (int i = 0; i < ThePipeline::MaxThreads; ++i) > - RAS[i].reset(); > - > - BP.reset(); > - BTB.reset(); > -*/ > -} > - > - > -bool > -BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid) > -{ > - // See if branch predictor predicts taken. > - // If so, get its target addr either from the BTB or the RAS. > - // Save off record of branch stuff so the RAS can be fixed > - // up once it's done. > - > - using TheISA::MachInst; > - > - int asid = inst->asid; > - bool pred_taken = false; > - TheISA::PCState target; > - > - ++lookups; > - DPRINTF(InOrderBPred, "[tid:%i] [sn:%i] %s ... PC %s doing branch " > - "predictionn", tid, inst->seqNum, > - inst->staticInst->disassemble(inst->instAddr()), > - inst->pcState()); > - > - > - void *bp_history = NULL; > - > - if (inst->isUncondCtrl()) { > - DPRINTF(InOrderBPred, "[tid:%i] Unconditional control.n", > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev [2] Links: ------ [1] http://repo.gem5.org/gem5?cmd=changeset;node=d059f8a95a42 [2] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
