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Ship it! >From my side is fine. I can imagine it shakes some stats around though... - Andreas Hansson On Feb. 1, 2013, 5:48 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1683/ > ----------------------------------------------------------- > > (Updated Feb. 1, 2013, 5:48 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9507:1b6c00205a89 > --------------------------- > ruby: enable multiple clock domanins > This patch allows ruby to have multiple clock domains. As I understand > with this patch, controllers can have different frequencies. The entire > network needs to run at a single frequency. > > The idea is that with in an object, time is treated in terms of cycles. > But the messages that are passed from one entity to another should contain > the time in Ticks. As of now, this is only true for the message buffers, > but not for the links in the network. As I understand the code, all the > entities in different networks (simple, garnet-fixed, garnet-flexible) should > be clocked at the same frequency. > > Another problem is that the directory controller has to operate at the same > frequency as the ruby system. This is because the memory controller does > not make use of the Message Buffer, and instead implements a buffer of its > own. So, it has no idea of the frequency at which the directory controller > is operating and uses ruby system's frequency for scheduling events. > > > Diffs > ----- > > src/mem/ruby/buffers/MessageBuffer.cc 890fc69ba53c > src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc > 890fc69ba53c > src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc > 890fc69ba53c > src/mem/ruby/network/simple/Throttle.cc 890fc69ba53c > src/mem/ruby/profiler/Profiler.cc 890fc69ba53c > src/mem/ruby/slicc_interface/Message.hh 890fc69ba53c > src/mem/ruby/slicc_interface/NetworkMessage.hh 890fc69ba53c > src/mem/ruby/slicc_interface/RubyRequest.hh 890fc69ba53c > src/mem/ruby/system/DMASequencer.cc 890fc69ba53c > src/mem/ruby/system/RubyMemoryControl.cc 890fc69ba53c > src/mem/ruby/system/Sequencer.cc 890fc69ba53c > src/mem/ruby/system/System.hh 890fc69ba53c > src/mem/ruby/system/WireBuffer.cc 890fc69ba53c > src/mem/slicc/ast/EnqueueStatementAST.py 890fc69ba53c > src/mem/slicc/symbols/Type.py 890fc69ba53c > > Diff: http://reviews.gem5.org/r/1683/diff/ > > > Testing > ------- > > Regressions pass. Patch has been tested very lightly using the ruby random > tester. > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
