changeset b03b556a8fbb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b03b556a8fbb
description:
ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer
class.
But to get ruby to compile, the rest of the changes had to be carried
out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 6 +-
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 6 +-
src/mem/protocol/MESI_CMP_directory-dir.sm | 4 +-
src/mem/protocol/MESI_CMP_directory-dma.sm | 2 +-
src/mem/protocol/MI_example-cache.sm | 4 +-
src/mem/protocol/MI_example-dir.sm | 2 +-
src/mem/protocol/MI_example-dma.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 5 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 4 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 4 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 34 ++++---
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 4 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 9 +-
src/mem/protocol/MOESI_CMP_token-dma.sm | 2 +-
src/mem/protocol/MOESI_hammer-cache.sm | 6 +-
src/mem/protocol/MOESI_hammer-dir.sm | 2 +-
src/mem/protocol/MOESI_hammer-dma.sm | 2 +-
src/mem/protocol/Network_test-cache.sm | 2 +-
src/mem/protocol/RubySlicc_Exports.sm | 1 +
src/mem/protocol/RubySlicc_Types.sm | 2 +-
src/mem/protocol/RubySlicc_Util.sm | 1 +
src/mem/ruby/buffers/MessageBuffer.cc | 28 +++---
src/mem/ruby/buffers/MessageBuffer.hh | 18 +--
src/mem/ruby/buffers/MessageBufferNode.hh | 18 +--
src/mem/ruby/common/Consumer.cc | 7 +-
src/mem/ruby/common/Consumer.hh | 5 +-
src/mem/ruby/network/BasicLink.hh | 2 +-
src/mem/ruby/network/BasicLink.py | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 10 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc | 6 +-
src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc | 2 +-
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py | 2 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 12 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh | 3 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc | 16 ++-
src/mem/ruby/network/garnet/flexible-pipeline/Router.hh | 2 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 2 +-
src/mem/ruby/network/simple/Switch.cc | 6 +-
src/mem/ruby/network/simple/Switch.hh | 2 +-
src/mem/ruby/network/simple/Throttle.cc | 10 +-
src/mem/ruby/network/simple/Throttle.hh | 17 +--
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 2 -
src/mem/ruby/slicc_interface/AbstractController.hh | 2 +-
src/mem/ruby/slicc_interface/Controller.py | 2 +-
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 5 +-
src/mem/ruby/system/Cache.py | 2 +-
src/mem/ruby/system/CacheMemory.hh | 4 +-
src/mem/ruby/system/RubyMemoryControl.cc | 4 +-
src/mem/ruby/system/RubyMemoryControl.hh | 6 +-
src/mem/ruby/system/RubyMemoryControl.py | 6 +-
src/mem/ruby/system/Sequencer.cc | 2 +-
src/mem/ruby/system/TimerTable.cc | 5 +-
src/mem/ruby/system/TimerTable.hh | 7 +-
src/mem/ruby/system/WireBuffer.cc | 12 +-
src/mem/ruby/system/WireBuffer.hh | 2 +-
src/mem/slicc/ast/EnqueueStatementAST.py | 6 +-
src/mem/slicc/ast/FuncCallExprAST.py | 4 +-
src/mem/slicc/ast/InfixOperatorExprAST.py | 43
+++++----
src/mem/slicc/symbols/StateMachine.py | 13 +-
src/mem/slicc/symbols/Type.py | 2 +
67 files changed, 218 insertions(+), 199 deletions(-)
diffs (truncated from 1546 to 300 lines):
diff -r 66eb324d4de1 -r b03b556a8fbb
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -33,9 +33,9 @@
CacheMemory * L1DcacheMemory,
Prefetcher * prefetcher = 'NULL',
int l2_select_num_bits,
- int l1_request_latency = 2,
- int l1_response_latency = 2,
- int to_l2_latency = 1,
+ Cycles l1_request_latency = 2,
+ Cycles l1_response_latency = 2,
+ Cycles to_l2_latency = 1,
bool send_evictions,
bool enable_prefetch = "False"
{
diff -r 66eb324d4de1 -r b03b556a8fbb
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -34,9 +34,9 @@
machine(L2Cache, "MESI Directory L2 Cache CMP")
: CacheMemory * L2cacheMemory,
- int l2_request_latency = 2,
- int l2_response_latency = 2,
- int to_l1_latency = 1
+ Cycles l2_request_latency = 2,
+ Cycles l2_response_latency = 2,
+ Cycles to_l1_latency = 1
{
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Sun Feb 10 21:26:24
2013 -0600
@@ -38,8 +38,8 @@
machine(Directory, "MESI_CMP_filter_directory protocol")
: DirectoryMemory * directory,
MemoryControl * memBuffer,
- int to_mem_ctrl_latency = 1,
- int directory_latency = 6
+ Cycles to_mem_ctrl_latency = 1,
+ Cycles directory_latency = 6
{
MessageBuffer requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type="request";
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm Sun Feb 10 21:26:24
2013 -0600
@@ -29,7 +29,7 @@
machine(DMA, "DMA Controller")
: DMASequencer * dma_sequencer,
- int request_latency = 6
+ Cycles request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response", no_vector="true";
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Sun Feb 10 21:26:23 2013 -0600
+++ b/src/mem/protocol/MI_example-cache.sm Sun Feb 10 21:26:24 2013 -0600
@@ -30,8 +30,8 @@
machine(L1Cache, "MI Example L1 Cache")
: Sequencer * sequencer,
CacheMemory * cacheMemory,
- int cache_response_latency = 12,
- int issue_latency = 2,
+ Cycles cache_response_latency = 12,
+ Cycles issue_latency = 2,
bool send_evictions
{
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Sun Feb 10 21:26:23 2013 -0600
+++ b/src/mem/protocol/MI_example-dir.sm Sun Feb 10 21:26:24 2013 -0600
@@ -30,7 +30,7 @@
machine(Directory, "Directory protocol")
: DirectoryMemory * directory,
MemoryControl * memBuffer,
- int directory_latency = 12
+ Cycles directory_latency = 12
{
MessageBuffer forwardFromDir, network="To", virtual_network="3",
ordered="false", vnet_type="forward";
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Sun Feb 10 21:26:23 2013 -0600
+++ b/src/mem/protocol/MI_example-dma.sm Sun Feb 10 21:26:24 2013 -0600
@@ -29,7 +29,7 @@
machine(DMA, "DMA Controller")
: DMASequencer * dma_sequencer,
- int request_latency = 6
+ Cycles request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response", no_vector="true";
diff -r 66eb324d4de1 -r b03b556a8fbb
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -37,7 +37,8 @@
CacheMemory * L1IcacheMemory,
CacheMemory * L1DcacheMemory,
int l2_select_num_bits,
- int request_latency = 2,
+ Cycles request_latency = 2,
+ Cycles use_timeout_latency = 50,
bool send_evictions
{
@@ -696,7 +697,7 @@
}
action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") {
- useTimerTable.set(address, 50);
+ useTimerTable.set(address, use_timeout_latency);
}
action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
diff -r 66eb324d4de1 -r b03b556a8fbb
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -34,8 +34,8 @@
machine(L2Cache, "Token protocol")
: CacheMemory * L2cacheMemory,
- int response_latency = 2,
- int request_latency = 2
+ Cycles response_latency = 2,
+ Cycles request_latency = 2
{
// L2 BANK QUEUES
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Sun Feb 10 21:26:24
2013 -0600
@@ -33,7 +33,7 @@
machine(Directory, "Directory protocol")
: DirectoryMemory * directory,
MemoryControl * memBuffer,
- int directory_latency = 6
+ Cycles directory_latency = 6
{
// ** IN QUEUES **
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Sun Feb 10 21:26:24
2013 -0600
@@ -1,8 +1,8 @@
machine(DMA, "DMA Controller")
: DMASequencer * dma_sequencer,
- int request_latency = 14,
- int response_latency = 14
+ Cycles request_latency = 14,
+ Cycles response_latency = 14
{
MessageBuffer responseFromDir, network="From", virtual_network="2",
ordered="false", vnet_type="response";
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -38,10 +38,14 @@
CacheMemory * L1DcacheMemory,
int l2_select_num_bits,
int N_tokens,
- int l1_request_latency = 2,
- int l1_response_latency = 2,
+
+ Cycles l1_request_latency = 2,
+ Cycles l1_response_latency = 2,
int retry_threshold = 1,
- int fixed_timeout_latency = 100,
+ Cycles fixed_timeout_latency = 100,
+ Cycles reissue_wakeup_latency = 10,
+ Cycles use_timeout_latency = 50,
+
bool dynamic_timeout_enabled = true,
bool no_mig_atomic = true,
bool send_evictions
@@ -195,19 +199,20 @@
int outstandingRequests, default="0";
int outstandingPersistentRequests, default="0";
- int averageLatencyHysteresis, default="(8)"; // Constant that provides
hysteresis for calculated the estimated average
- int averageLatencyCounter, default="(500 <<
(*m_L1Cache_averageLatencyHysteresis_ptr))";
+ // Constant that provides hysteresis for calculated the estimated average
+ int averageLatencyHysteresis, default="(8)";
+ Cycles averageLatencyCounter,
+ default="(Cycles(500) << (*m_L1Cache_averageLatencyHysteresis_ptr))";
- int averageLatencyEstimate() {
+ Cycles averageLatencyEstimate() {
DPRINTF(RubySlicc, "%d\n",
(averageLatencyCounter >> averageLatencyHysteresis));
//profile_average_latency_estimate( (averageLatencyCounter >>
averageLatencyHysteresis) );
return averageLatencyCounter >> averageLatencyHysteresis;
}
- void updateAverageLatencyEstimate(int latency) {
+ void updateAverageLatencyEstimate(Cycles latency) {
DPRINTF(RubySlicc, "%d\n", latency);
- assert(latency >= 0);
// By subtracting the current average and then adding the most
// recent sample, we calculate an estimate of the recent average.
@@ -781,7 +786,7 @@
// IssueCount.
// Set a wakeup timer
- reissueTimerTable.set(address, 10);
+ reissueTimerTable.set(address, reissue_wakeup_latency);
}
} else {
@@ -834,7 +839,7 @@
// Set a wakeup timer
if (dynamic_timeout_enabled) {
- reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
+ reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4);
} else {
reissueTimerTable.set(address, fixed_timeout_latency);
}
@@ -902,10 +907,9 @@
// IssueCount.
// Set a wakeup timer
- reissueTimerTable.set(address, 10);
+ reissueTimerTable.set(address, reissue_wakeup_latency);
}
-
} else {
// Make a normal request
enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
@@ -961,7 +965,7 @@
// Set a wakeup timer
if (dynamic_timeout_enabled) {
- reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
+ reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4);
} else {
reissueTimerTable.set(address, fixed_timeout_latency);
}
@@ -1381,7 +1385,7 @@
}
action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
- useTimerTable.set(address, 50);
+ useTimerTable.set(address, use_timeout_latency);
}
action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all
tokens") {
@@ -1448,7 +1452,7 @@
// Update average latency
if (tbe.IssueCount <= 1) {
if (tbe.ExternalResponse == true) {
- updateAverageLatencyEstimate(time_to_int(curCycle()) -
time_to_int(tbe.IssueTime));
+ updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime));
}
}
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Sun Feb 10 21:26:23
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Sun Feb 10 21:26:24
2013 -0600
@@ -35,8 +35,8 @@
machine(L2Cache, "Token protocol")
: CacheMemory * L2cacheMemory,
int N_tokens,
- int l2_request_latency = 5,
- int l2_response_latency = 5,
+ Cycles l2_request_latency = 5,
+ Cycles l2_response_latency = 5,
bool filtering_enabled = true
{
diff -r 66eb324d4de1 -r b03b556a8fbb src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Sun Feb 10 21:26:23 2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Sun Feb 10 21:26:24 2013 -0600
@@ -36,9 +36,10 @@
: DirectoryMemory * directory,
MemoryControl * memBuffer,
int l2_select_num_bits,
- int directory_latency = 5,
+ Cycles directory_latency = 5,
bool distributed_persistent = true,
- int fixed_timeout_latency = 100
+ Cycles fixed_timeout_latency = 100,
+ Cycles reissue_wakeup_latency = 10
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="5",
ordered="true", vnet_type="response";
@@ -470,7 +471,7 @@
// IssueCount.
// Set a wakeup timer
- reissueTimerTable.set(address, 10);
+ reissueTimerTable.set(address, reissue_wakeup_latency);
}
}
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