[gem5-dev] changeset in gem5: ARM: fix some cases where instructions that w...

[Ali Saidi]

changeset cac6e95e236c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cac6e95e236c
description:
        ARM: fix some cases where instructions that write to fp reg 15 are 
accidently branches.

diffstat:

 src/arch/arm/isa/templates/mem.isa  |  8 ++++----
 src/arch/arm/isa/templates/pred.isa |  4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diffs (60 lines):

diff -r 13ae8000f771 -r cac6e95e236c src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa        Sat Mar 02 23:12:55 2013 -0600
+++ b/src/arch/arm/isa/templates/mem.isa        Mon Mar 04 23:33:47 2013 -0500
@@ -1122,7 +1122,7 @@
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             IntRegIndex wbIndexReg = index;
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                        _shiftAmt, _shiftType, _index);
@@ -1156,7 +1156,7 @@
 
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)
@@ -1185,7 +1185,7 @@
 #if %(use_uops)d
         assert(numMicroops >= 2);
         uops = new StaticInstPtr[numMicroops];
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
                                    _imm);
             uops[0]->setDelayedCommit();
@@ -1208,7 +1208,7 @@
             uops[1]->setLastMicroop();
         }
 #else
-        if (_dest == INTREG_PC) {
+        if (_dest == INTREG_PC && !isFloating()) {
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (conditional)
diff -r 13ae8000f771 -r cac6e95e236c src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa       Sat Mar 02 23:12:55 2013 -0600
+++ b/src/arch/arm/isa/templates/pred.isa       Mon Mar 04 23:33:47 2013 -0500
@@ -77,7 +77,7 @@
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
@@ -117,7 +117,7 @@
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
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