Thanks Nilay for checking this in. I know this is a small patch, but there was a lot of previous effort on your part to make it happen.
Going forward, I do think it is important to make the backing store optional and not remove it completely. I'm fine if we maintain the default as off, but there are a few times when it is nice to leverage the backing store for simple boundary experiments. So if we want to enable the backing store for se mode, is it as simple as setting access_phys_mem to true and setting the system.physmem.null to true? Can we modify the se.py/Ruby.py to do this using just one command line parameter? Nilay, I'm still in the midst of a significant rebase of our tree due to your clock/time changes. Please hold off on checking any more Ruby changes until I can get our patches out the door. Thanks, Brad -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Nilay Vaish Sent: Wednesday, March 06, 2013 7:53 PM To: [email protected] Subject: [gem5-dev] changeset in gem5: ruby: remove the functional copy of memory in... changeset 91cac7c9c636 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=91cac7c9c636 description: ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. diffstat: configs/example/ruby_fs.py | 2 ++ configs/example/se.py | 3 +++ src/mem/ruby/system/Sequencer.py | 4 +++- tests/configs/memtest-ruby.py | 10 ++-------- tests/configs/pc-simple-timing-ruby.py | 3 +++ tests/configs/rubytest-ruby.py | 8 +------- tests/configs/simple-timing-ruby.py | 2 +- 7 files changed, 15 insertions(+), 17 deletions(-) diffs (125 lines): diff -r 2c094ad4dc70 -r 91cac7c9c636 configs/example/ruby_fs.py --- a/configs/example/ruby_fs.py Wed Mar 06 21:53:16 2013 -0600 +++ b/configs/example/ruby_fs.py Wed Mar 06 21:53:57 2013 -0600 @@ -114,5 +114,7 @@ cpu.interrupts.int_master = system.piobus.slave cpu.interrupts.int_slave = system.piobus.master + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) Simulation.run(options, root, system, FutureClass) diff -r 2c094ad4dc70 -r 91cac7c9c636 configs/example/se.py --- a/configs/example/se.py Wed Mar 06 21:53:16 2013 -0600 +++ b/configs/example/se.py Wed Mar 06 21:53:57 2013 -0600 @@ -187,6 +187,9 @@ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) + # Set the option for physmem so that it is not allocated any space + system.physmem.null = True + options.use_map = True Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) diff -r 2c094ad4dc70 -r 91cac7c9c636 src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py Wed Mar 06 21:53:16 2013 -0600 +++ b/src/mem/ruby/system/Sequencer.py Wed Mar 06 21:53:57 2013 -0600 @@ -41,7 +41,7 @@ pio_port = MasterPort("Ruby_pio_port") using_ruby_tester = Param.Bool(False, "") using_network_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(True, + access_phys_mem = Param.Bool(False, "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") system = Param.System(Parent.any, "system object") @@ -52,6 +52,7 @@ class RubyPortProxy(RubyPort): type = 'RubyPortProxy' cxx_header = "mem/ruby/system/RubyPortProxy.hh" + access_phys_mem = True class RubySequencer(RubyPort): type = 'RubySequencer' @@ -67,3 +68,4 @@ class DMASequencer(RubyPort): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" + access_phys_mem = True diff -r 2c094ad4dc70 -r 91cac7c9c636 tests/configs/memtest-ruby.py --- a/tests/configs/memtest-ruby.py Wed Mar 06 21:53:16 2013 -0600 +++ b/tests/configs/memtest-ruby.py Wed Mar 06 21:53:57 2013 -0600 @@ -79,8 +79,8 @@ # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), - physmem = SimpleMemory()) + physmem = SimpleMemory(null = True), + funcbus = NoncoherentBus()) Ruby.create_system(options, system) @@ -100,12 +100,6 @@ # ruby_port.deadlock_threshold = 1000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # connect reference memory to funcbus system.funcmem.port = system.funcbus.master diff -r 2c094ad4dc70 -r 91cac7c9c636 tests/configs/pc-simple-timing-ruby.py --- a/tests/configs/pc-simple-timing-ruby.py Wed Mar 06 21:53:16 2013 -0600 +++ b/tests/configs/pc-simple-timing-ruby.py Wed Mar 06 21:53:57 2013 -0600 @@ -74,5 +74,8 @@ cpu.interrupts.int_slave = system.piobus.master cpu.clock = '2GHz' + # Set access_phys_mem to True for ruby port + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') diff -r 2c094ad4dc70 -r 91cac7c9c636 tests/configs/rubytest-ruby.py --- a/tests/configs/rubytest-ruby.py Wed Mar 06 21:53:16 2013 -0600 +++ b/tests/configs/rubytest-ruby.py Wed Mar 06 21:53:57 2013 -0600 @@ -77,7 +77,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, wakeup_frequency = 10, num_cpus = options.num_cpus) -system = System(tester = tester, physmem = SimpleMemory()) +system = System(tester = tester, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) @@ -104,12 +104,6 @@ # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff -r 2c094ad4dc70 -r 91cac7c9c636 tests/configs/simple-timing-ruby.py --- a/tests/configs/simple-timing-ruby.py Wed Mar 06 21:53:16 2013 -0600 +++ b/tests/configs/simple-timing-ruby.py Wed Mar 06 21:53:57 2013 -0600 @@ -67,7 +67,7 @@ options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory()) +system = System(cpu = cpu, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
