changeset f9b731fc6064 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f9b731fc6064
description:
slicc: remove check if the L1Cache has a sequencer
diffstat:
src/mem/slicc/symbols/StateMachine.py | 15 ++-------------
1 files changed, 2 insertions(+), 13 deletions(-)
diffs (25 lines):
diff -r aa73a81cf92c -r f9b731fc6064 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Fri Mar 22 15:53:24 2013 -0500
+++ b/src/mem/slicc/symbols/StateMachine.py Fri Mar 22 15:53:24 2013 -0500
@@ -482,19 +482,8 @@
# For the l1 cache controller, add the special atomic support which
# includes passing the sequencer a pointer to the controller.
#
- if self.ident == "L1Cache":
- if not sequencers:
- self.error("The L1Cache controller must include the sequencer
" \
- "configuration parameter")
-
- for seq in sequencers:
- code('''
-m_${{seq}}_ptr->setController(this);
- ''')
-
- else:
- for seq in sequencers:
- code('''
+ for seq in sequencers:
+ code('''
m_${{seq}}_ptr->setController(this);
''')
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