changeset daa8a14ec85e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=daa8a14ec85e
description:
stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 58 +++++-----
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 56 ++++----
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 58 +++++-----
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 2 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 58 +++++-----
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 58 +++++-----
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 58 +++++-----
7 files changed, 174 insertions(+), 174 deletions(-)
diffs (truncated from 587 to 300 lines):
diff -r c35b47fd0df8 -r daa8a14ec85e
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Mar 26 14:46:51 2013 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Tue Mar 26 14:47:03 2013 -0400
@@ -4,11 +4,11 @@
sim_ticks 1897807508000 #
Number of ticks simulated
final_tick 1897807508000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 93562 #
Simulator instruction rate (inst/s)
-host_op_rate 93562 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3130145601 #
Simulator tick rate (ticks/s)
-host_mem_usage 338704 #
Number of bytes of host memory used
-host_seconds 606.30 #
Real time elapsed on the host
+host_inst_rate 94343 #
Simulator instruction rate (inst/s)
+host_op_rate 94343 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3156287920 #
Simulator tick rate (ticks/s)
+host_mem_usage 338708 #
Number of bytes of host memory used
+host_seconds 601.28 #
Real time elapsed on the host
sim_insts 56726638 #
Number of instructions simulated
sim_ops 56726638 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 852800 #
Number of bytes read from this memory
@@ -512,12 +512,12 @@
system.iocache.overall_misses::total 41729 #
number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21380998
# number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21380998
# number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10586785423
# number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10586785423
# number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10608166421
# number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10608166421 #
number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10608166421
# number of overall miss cycles
-system.iocache.overall_miss_latency::total 10608166421
# number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10586787421
# number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10586787421
# number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10608168419
# number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10608168419 #
number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10608168419
# number of overall miss cycles
+system.iocache.overall_miss_latency::total 10608168419
# number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 177
# number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 177 #
number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552
# number of WriteReq accesses(hits+misses)
@@ -536,12 +536,12 @@
system.iocache.overall_miss_rate::total 1 #
miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870
# average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120796.598870
# average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.015763
# average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 254784.015763
# average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 254215.687436
# average overall miss latency
-system.iocache.demand_avg_miss_latency::total 254215.687436
# average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 254215.687436
# average overall miss latency
-system.iocache.overall_avg_miss_latency::total 254215.687436
# average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.063848
# average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 254784.063848
# average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 254215.735316
# average overall miss latency
+system.iocache.demand_avg_miss_latency::total 254215.735316
# average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 254215.735316
# average overall miss latency
+system.iocache.overall_avg_miss_latency::total 254215.735316
# average overall miss latency
system.iocache.blocked_cycles::no_mshrs 281558 #
number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.iocache.blocked::no_mshrs 26875 #
number of cycles access was blocked
@@ -562,12 +562,12 @@
system.iocache.overall_mshr_misses::total 41729 #
number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249
# number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12176249
# number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424787682
# number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8424787682
# number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8436963931
# number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8436963931
# number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8436963931
# number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8436963931
# number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424789680
# number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8424789680
# number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8436965929
# number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8436965929
# number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8436965929
# number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8436965929
# number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1
# mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for WriteReq accesses
@@ -578,12 +578,12 @@
system.iocache.overall_mshr_miss_rate::total 1
# mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232
# average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232
# average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.880295
# average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.880295
# average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.666084
# average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 202184.666084
# average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.666084
# average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 202184.666084
# average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.928379
# average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.928379
# average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.713964
# average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 202184.713964
# average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.713964
# average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 202184.713964
# average overall mshr miss latency
system.iocache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 #
Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 #
Number of bytes transfered via DMA reads (not PRD).
diff -r c35b47fd0df8 -r daa8a14ec85e
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Tue Mar
26 14:46:51 2013 -0400
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Tue Mar
26 14:47:03 2013 -0400
@@ -4,11 +4,11 @@
sim_ticks 1854310449000 #
Number of ticks simulated
final_tick 1854310449000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 95500 #
Simulator instruction rate (inst/s)
-host_op_rate 95500 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3343297346 #
Simulator tick rate (ticks/s)
+host_inst_rate 91767 #
Simulator instruction rate (inst/s)
+host_op_rate 91767 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3212612251 #
Simulator tick rate (ticks/s)
host_mem_usage 333588 #
Number of bytes of host memory used
-host_seconds 554.64 #
Real time elapsed on the host
+host_seconds 577.20 #
Real time elapsed on the host
sim_insts 52967561 #
Number of instructions simulated
sim_ops 52967561 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 964416 #
Number of bytes read from this memory
@@ -200,12 +200,12 @@
system.iocache.overall_misses::total 41725 #
number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998
# number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998
# number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10634243420
# number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10634243420
# number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10655171418
# number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10655171418 #
number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10655171418
# number of overall miss cycles
-system.iocache.overall_miss_latency::total 10655171418
# number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10634247416
# number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10634247416
# number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10655175414
# number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10655175414 #
number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10655175414
# number of overall miss cycles
+system.iocache.overall_miss_latency::total 10655175414
# number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173
# number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 #
number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552
# number of WriteReq accesses(hits+misses)
@@ -224,12 +224,12 @@
system.iocache.overall_miss_rate::total 1 #
miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705
# average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705
# average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.150847
# average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 255926.150847
# average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255366.600791
# average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255366.600791
# average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255366.600791
# average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255366.600791
# average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.247016
# average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 255926.247016
# average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255366.696561
# average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255366.696561
# average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255366.696561
# average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255366.696561
# average overall miss latency
system.iocache.blocked_cycles::no_mshrs 283342 #
number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.iocache.blocked::no_mshrs 27068 #
number of cycles access was blocked
@@ -250,12 +250,12 @@
system.iocache.overall_mshr_misses::total 41725 #
number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249
# number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249
# number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472243194
# number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8472243194
# number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8484174443
# number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8484174443
# number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8484174443
# number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8484174443
# number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472247190
# number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8472247190
# number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8484178439
# number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8484178439
# number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8484178439
# number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8484178439
# number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1
# mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for WriteReq accesses
@@ -266,12 +266,12 @@
system.iocache.overall_mshr_miss_rate::total 1
# mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225
# average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225
# average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203894.955574
# average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203894.955574
# average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.516908
# average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203335.516908
# average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.516908
# average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203335.516908
# average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203895.051742
# average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 203895.051742
# average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.612678
# average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203335.612678
# average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.612678
# average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203335.612678
# average overall mshr miss latency
system.iocache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 #
Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 #
Number of bytes transfered via DMA reads (not PRD).
diff -r c35b47fd0df8 -r daa8a14ec85e
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Tue Mar
26 14:46:51 2013 -0400
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Tue Mar
26 14:47:03 2013 -0400
@@ -4,11 +4,11 @@
sim_ticks 5136864508000 #
Number of ticks simulated
final_tick 5136864508000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 161248 #
Simulator instruction rate (inst/s)
-host_op_rate 318747 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2030694494 #
Simulator tick rate (ticks/s)
-host_mem_usage 783308 #
Number of bytes of host memory used
-host_seconds 2529.61 #
Real time elapsed on the host
+host_inst_rate 157360 #
Simulator instruction rate (inst/s)
+host_op_rate 311060 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1981722494 #
Simulator tick rate (ticks/s)
+host_mem_usage 783288 #
Number of bytes of host memory used
+host_seconds 2592.12 #
Real time elapsed on the host
sim_insts 407895398 #
Number of instructions simulated
sim_ops 806304609 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2499136
# Number of bytes read from this memory
@@ -208,12 +208,12 @@
system.iocache.overall_misses::total 47629 #
number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144901871
# number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 144901871
# number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053195615
# number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10053195615
# number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10198097486
# number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10198097486 #
number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10198097486
# number of overall miss cycles
-system.iocache.overall_miss_latency::total 10198097486
# number of overall miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053199611
# number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10053199611
# number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10198101482
# number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10198101482 #
number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10198101482
# number of overall miss cycles
+system.iocache.overall_miss_latency::total 10198101482
# number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 909
# number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 909 #
number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720
# number of WriteReq accesses(hits+misses)
@@ -232,12 +232,12 @@
system.iocache.overall_miss_rate::total 1 #
miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900
# average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 159407.998900
# average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.700664
# average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 215179.700664
# average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.297109
# average overall miss latency
-system.iocache.demand_avg_miss_latency::total 214115.297109
# average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.297109
# average overall miss latency
-system.iocache.overall_avg_miss_latency::total 214115.297109
# average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.786194
# average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 215179.786194
# average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.381007
# average overall miss latency
+system.iocache.demand_avg_miss_latency::total 214115.381007
# average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.381007
# average overall miss latency
+system.iocache.overall_avg_miss_latency::total 214115.381007
# average overall miss latency
system.iocache.blocked_cycles::no_mshrs 138033 #
number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.iocache.blocked::no_mshrs 12531 #
number of cycles access was blocked
@@ -258,12 +258,12 @@
system.iocache.overall_mshr_misses::total 47629 #
number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97611900
# number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 97611900
# number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622408830
# number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7622408830
# number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720020730
# number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7720020730
# number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720020730
# number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7720020730
# number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622412826
# number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7622412826
# number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720024726
# number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7720024726
# number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720024726
# number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7720024726
# number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1
# mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1
# mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1
# mshr miss rate for WriteReq accesses
@@ -274,12 +274,12 @@
system.iocache.overall_mshr_miss_rate::total 1
# mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide
107383.828383 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383
# average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide
163150.873930 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.873930
# average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.559239
# average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162086.559239
# average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide
162086.559239 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162086.559239
# average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide
163150.959461 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.959461
# average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138
# average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 162086.643138
# average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide
162086.643138 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 162086.643138
# average overall mshr miss latency
system.iocache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0
# Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816
# Number of bytes transfered via DMA reads (not PRD).
diff -r c35b47fd0df8 -r daa8a14ec85e
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt Tue Mar 26
14:46:51 2013 -0400
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt Tue Mar 26
14:47:03 2013 -0400
@@ -408,7 +408,7 @@
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 #
Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 #
Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7
# Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4656763 #
Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 4656762 #
Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 #
Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 69891405 #
Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 28868892 #
Number of cycles IEW is blocking
diff -r c35b47fd0df8 -r daa8a14ec85e
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
